Andes Webinar

Webinar Series: Next-Generation Vector Processor Design #4

Sep 29 (Wed.)
9:00 AM (PDT)

Sep 30 (Thu.)
2:00 PM (GMT+8)

Upcoming Webinar

Next-Generation Vector Processor Design IV: Simplifying Complex RISC-V Vector Extension Memory Operations

 Sep 29 & Sep 30
 Speaker: Dr. Thang Tran, Principle Architect of Andes Technology Corp.
 English: Sep 29 @9:00 AM (PST) →REGISTER← 
English: Sep 30 @2:00 PM (GMT+8) →REGISTER←


● What: Join Dr. Thang Tran, Principal Architect of Andes Technology and veteran of high-performance computing (HPC) for the last webinar in his four-part masterclass series on demystifying the RISC-V Vector extension. In this session, Dr. Tran will discuss all vector instructions which include compute, permutation, and memory operations. He will discuss the four basic types of memory operations: unit stride, constant stride, index, and segment.

● Who: Dr. Thang Tran, Principal Architect and veteran of high-performance computing (HPC) at Andes Technology Corp. will be the series' presenter. Dr. Tran is an industry expert in HPC development. He architected and designed the Andes RISC-V out-of-order (OOO) Vector Processor (VLEN/SIMD=512b) in 9 months using a revolutionary algorithm that does not resemble any previous known OOO superscalar design that has no temporary registers (not renaming, not re-order buffer).

● Why: Dr Tran's lecture will illustrate the most important feature of this vector processor: its simplicity. The vector processor issues 8 micro-ops per cycle with up to 14 vector instructions in parallel execution.

● Who should attend: SoC and ASIC chip architects, designers, and software developers.

On-demand Webinar

Next-Generation Vector Processor Design III: Demystifying RISC-V Vector Extension

Aug 30, 2021

Speaker: Dr. Thang Tran,  Principal Architect | English

The hour long event hosted by Andes Technology will be the third of a 4-part lecture series on next-generation vector processor design. It will showcase a 5-stage pipeline and an 8-stage in-order superscalar vector processor based on Andes’ latest AndeStar™ V5 Architecture. Both have design wins at major TSMC foundry customers.

Next-Generation Vector Processor Design II: Demystifying RISC-V Vector Extension

August 3, 2021

Speaker: Dr. Thang Tran,  Principal Architect | English

The hour long event hosted by Andes Technology will be the second of a 4-part lecture series on next-generation vector processor design. It will showcase a 5-stage pipeline and an 8-stage in-order superscalar vector processor based on Andes’ latest AndeStar™ V5 Architecture. Both have design wins at major TSMC foundry customers.

Next-Generation Vector Processor Design I

July 13, 2021

Speaker: Dr. Thang Tran,  Principal Architect | English

Join Dr. Thang Tran, Principal Architect of Andes Technology Corp. and veteran of high-performance computing (HPC), for the first of a 4-part lecture series on next-generation vector processor design. Dr. Tran is an industry expert in HPC development. He architected and designed the Andes RISC-V out-of-order (OOO) Vector Processor (VLEN/SIMD=512b) in 9 months using revolutionary algorithm that does not resemble any previous known OOO superscalar design that has no temporary registers (not renaming, not re-order buffer). The most important feature of this vector processor is simplicity. Andes NX27V issues 8 micro-ops per cycle with up to 14 vector instructions in parallel execution.

Embedded Solutions in IoV

June 1, 2021

Speaker: Frankwell Lin,  CEO | English

In COMPUTEX FORUM 2021, Andes CEO Frankwell Lin was invited to present “Embedded Solutions in IoV” for Future Car track and share the latest EV, IoV and automotive electronics trends.

 

Acceleration RISC-V AI and IoT Development with Andes Software Solutions

April 28, 2021

Speaker: Simon Wang, Technical Marketing Manager | English

AI and IoT applications are blooming everywhere. The products serving the market must not only be with good performance, high efficiency, and low power consumption to meet the constraints for computing and energy, but also need to be quick time-to-market to respond to the ever-changing market needs. Join us for 20-30 minutes to learn how Andes RISC-V software supports AI and IoT application developments. We will introduce the AndeSight™ IDE, BSP (Board Support Package), and the newly-launched NN, DSP and Vector libraries for accelerating computations as well as reducing the development schedule. Furthermore, we will present the benefits for AI, NN, DSP applications, and results from several benchmarks.

AndeSysC™-A Flexible RISC-V Processor Model for SoC Virtual Prototyping

March 25, 2021

Speaker: YiChiang Chang, Technical Marketing Manager | English

AndeSysC™ is Andes virtual platform solution based on SystemC to enrich the RISC-V ecosystem. It provides extendable, flexible and near-cycle accurate models of AndesCore™ V5 RISC-V processor IP’s and components for hardware designers to construct SoC prototypes and evaluate and verify their architecture, functionalities and performance before committing to the actual hardware implementation. With virtual models of Andes processors, AndeSight™ IDE and AndeSoft™ software stack, software engineers can jump-start their development on profiling, optimizing, debugging, and testing in parallel to hardware development to accelerate the development cycle of the complex design. 

In this talk, we will provide an overall picture of Andes and RISC-V momentum.  Then we will introduce the concept of the virtual prototyping and AndeSysC™ with a virtual SoC example that fully utilizes the features from AndeSight™ to expedite the development cycle.

Andes RISC V Processor IP Solutions

Jan 28, 2021

Speaker: Charlie Su, CTO & EVP | English

The SoC industry has seen the fast-growing and diversified demands for a wide range of RISC-V based products: from tiny low-power MCUs for consumer devices, to chips powering enterprise-grade products and datacenter servers; from one power-efficient core to a thousand GHz+ cores working cohesively. To serve the market, Andes has developed a rich portfolio of AndesCore processor IPs already used in the above scenarios. They include compact single-issue cores to feature-rich Linux-capable superscalar cores, cacheless single cores to cache-coherence multicores, and cores capable of processing floating-point and DSP data to those crunching a large volume of vector data. Based on the solid foundation, Andes continues to enrich our product offerings for higher performance efficiency as well as more flexible configurations.

In this talk, we will first give an overview of Andes existing V5 RISC-V processor lineup and present examples of how V5 processors are used in SoC. Then, we will introduce V5 IPs newly added to Andes processor portfolio, the associated software support and their performance data. We will provide an update of Andes Custom Extension™ (ACE) and show how it can further accelerate control and data paths in applications. We will conclude our talk with a summary.

An Introduction to RISC-V Vector Programming with C Intrinsic

Sep 17, 2020

Speaker: Chih-Mao Chen, Advanced Engineer | English

The “V” ISA extension for vector processing has been proposed to RISC-V to exploit data parallelism in domains such as machine learning and high-performance computing applications. In contrast to traditional SIMD processors with fixed-length vectors, the RISC-V vector extension defines a vector-length agnostic architecture where work is vectorized independently of a vector length that can be discovered at run-time. This is a departure from existing SIMD frameworks where the vector lengths are known statically, and a new intrinsic interface that takes advantage of scalable nature of RISC-V vectors is being developed by the community. This talk will provide an overview of the vector extension and how to program the vector processor, using Andes NX27V as an example, with C-level scalable vector types and intrinsic functions, as well as design choices and future evolution of the API.

RISC-V & SoC Architecture Exploration for AI & ML Many-core Compute Array

Aug 27, 2020

Speaker: John Min, Director of NA Field Application Engineering | English

This presentation will describe the first RISC-V Processor with Vector extension implemented in TSMC 7nm FF+ process. It will describe the applications adopting RISC-V with demanding real-time and high performance computing as well as machine learning application. The solution to be shown in this presentation has a die area of 0.3mm² and high performance clock speed of 1 GHz.

Andes Infuses into AI: High-Efficiency and High-Flexibility Processor IPs+NN SDK for AI

Jul 9, 2020

Speaker: John Min, Director of NA Field Application Engineering

To fulfill the diversity of AI applications (e.g., keyword spotting, object detection, etc.) in different environments including edge and cloud, Andes provides you with different choices to fit your AI targets with various requirements (computing power, power consumption, SRAM and code size). In this talk, Andes will introduce how RISC-V Packed-SIMD/DSP processors and RISC-V vector processors provide the high computing efficiency and flexibilities. Further with Andes NN SDK, it will be easy to integrate your AI applications to the shorter time-to-market, and achieve the outstanding utilization of hardware capabilities.

RISC-V Vector Extension and NX27V, the First Commercial RISC-V Vector Processor IP ​

May 21, 2020

Speaker: John Min, Director of NA Field Application Engineering

The applications of AI, AR/VR, computer vision, cryptography, and multimedia require high-speed processing of large volumes of data. A RISC-V processor with the powerful RISC-V Vector (RVV) extension instruction set and parallel execution capability can significantly accelerate the performance of those applications.

AndesCore™ NX27V is the first commercial RISC-V processor to support RVV scalable vector instruction set, designed from ground up to be a Cray-like full vector computation machine. The NX27V provides a Vector Register File (VRF) with each register as large as 512 bits. Its supports RVV standard data types such as integer, fixed point, and floating point as well as Andes-enhanced data types optimized for AI representations. The NX27V contains a scalar unit and a Vector Processing Unit (VPU). The VPU has multiple functional units, operating on inputs of up to 512 bits each cycle in parallel to sustain the computational throughput needed in diversified applications. For software development support, in addition to the compilation tools and the performance simulator, Andes also provides a powerful visualization tool for the NX27V to help analyze and optimize the performance of critical computation kernels.

Andes High Memory Efficiency 27 Series and Superscalar 45 Series CPU IP Cores​

May 7, 2020

Speaker: KY Hsieh, Senior Technical Manager

Inheriting technologies from its successful 25-series, AndesCore™ 27-series is Andes Technology’s second-generation RISC-V CPU IP solution. The recently released 32-bit A27 and 64-bit AX27 offer over 2 times higher bandwidth and deliver lower latency with its MemBoost technology, it is well suitable for memory-intensive applications, such as those run on Linux operating system.

The new 32/64-bit 45-series is an 8-stage in-order superscalar processor benefits from Andes’ proven 25-series cores, and compliant with the latest RISC-V specifications. It can issue two instructions per cycle and therefore significantly increases its performance. The superior pipelining results in world-class 5.4 Coremark/MHz, and can run up to 1.2GHz at 28nm in the worst case. The 45-series cores are ideal for embedded applications where response time and determinism are critical, such as 5G, AI, AR/VR, ADAS, IP surveillance, networking, storage, and V2X.

TWS (True Wireless Stereo) Solution Using Andes D25+ACE ​

Apr 23, 2020

Speaker: Tung Wei, Advanced Engineer

Andes D25, a power-efficient RISC-V CPU that supports P-extension for rich SIMD/DSP computation, is widely used in audio, voice, image and DSP applications. In addition, D25 is equipped with the powerful ACE (Andes Custom Extension™), which, by writing simple scripts and concise RTL codes, allows designers to new instructions to speed up critical functions and reduce power consumption at the same time.

TWS (True Wireless Stereo), a Bluetooth 5.0 technology, is expected to have continuous growth following leading vendors’ great success in their hot-selling TWS earphones. The challenge for SoC designers is to perform many complex computations fast and with low power consumption. In this webinar, we will introduce a unique solution for TWS based on D25 plus ACE acceleration. With the advantages of high flexibility, easy-to-integrate and low power, it perfectly addresses the requirements of TWS. It is the TWS solution you are looking for!

Andes Custom Extension™ - Accelerating Domain-Specific Architecture​

Apr 9, 2020

Speaker: Yi-Chiang Chang, Technical Manager

With greatly increase the requirements for domain-specific application from edge to cloud, designers are looking for hardware acceleration methods to fulfill their specific requirements.  In this webinar, YiChiang will introduce Andes Custom Extension™ (ACE) to help Andes’ customers convert the highly optimized Andes RISC-V V5 cores into domain-specific architecture to fulfill special acceleration.  He will also cover the major features of ACE and COPILOT, and share some practical examples for designers to accelerate their specific SW applications or algorithm by creating custom instructions through ACE.

Andes Software Solutions for RISC-V

Mar 26, 2020

Speaker: Niraj Dengale, Advanced Engineer

AndeSight™ integrated development environment provides a friendly software development interface when developing SoC with AndesCore™ CPUs. In the past 15 years, with customer feedback and continuous product improvement, AndeSight™ has developed comprehensive functions. As for AndeSoft™ BSP, it provides a wealth of software projects under the command line, such as toolchain, bare metal demo programs, RTOS/Linux and DSP library related software.

Andes RISC-V V5 CPUs​

Mar 12, 2020

Speaker: Tung Wei, Advanced Engineer

Introduction to Andes RISC-V CPU cores lineup, Andes Custom Extensions (ACE), software supports from bare metal to Linux, and Integrated Development Environment (IDE). People who join this webinar will learn what Andes could help designers to create highly competitive domain-specific SoCs easily.

Topics Covered in RISC-V CON

- The powerful AndesCore™ V5, D25, 27-series, 45-series
- The cutting edge Andes RISC-V vector extension processor
- The leading solution Andes Custom Extension™
- The diverse AI applications of RISC-V
- The latest market trends and technology of RISC-V
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