AndesCore™ N22

Ultra Compact 32-bit RISC-V CPU Core

AndesCore™ N22 Overview

  • AndeStar™ V5/V5e Instruction Set Architecture (ISA), compliant to RISC-V technology
  • Support RV32IMAC/EMAC
  • Andes extensions, architected for performance and functionality enhancements
  • 32-bit, 2-stage pipeline CPU architecture
  • 16/32-bit mixable instruction format for compacting code density
  • Branch predication to speed up control code
  • Configurable Multipiler
  • Physical Memory Protection (PMP)
  • Core-Local Interrupt Controller (CLIC) with selective vectoring and priority preemption 
  • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting SoC with multiple processors 
  • Advanced CoDense™ technology to reduce program code size
  • StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
  • Several configurations to tradeoff between core size and performance requirements

AndesCore™ N22 is a 32-bit 2-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications that require low energy consumption and small area. It is compliant to RISC-V technology with several efficient performance features, including simple dynamic branch prediction, instruction cache, and local memories. It supports 32 or 16 general purpose registers (GPRs) and fast or small multiplier for performance/area tradeoff. In addition, it comes with rich optional features to ease SoC integration such as vectored CLIC and PLIC for design flexibility, AHB-Lite 32-bit bus for system integration, Fast I/O interface for low latency accesses, APB for CPU local peripherals, PowerBrake and WFI/WFE mode for low power and power management, and JTAG debug interface for development support.

Applications

  • Sensor fusion
  • Smart Meter
  • Small IoT devices
  • Wearable devices
  • Toy and electronic education equipment

Block Diagram

Development Tools

  • AndeSight™ Integrated Development Environment
  • ICE debugging hardware

Key Features and Performance

AndeStar™ V5 Architecture

Key FeaturesBenefits
RISC-V RV32IMAC Instructions
  • State-of-the art ISA from latest developments in computer architecture
  • Industry standard and open architecture
Andes Extended Instructions Andes exclusive performance and functionality enhancements
16/32-bit mixable instruction format For compact code density
16 or 32 general-purpose registers For better code size and performance
Machine (M) and User (U) Privilege levels Embedded systems with privilege protections

CPU Core

Key FeaturesBenefits
1.80 DMIPS/MHz, 3.97 CoreMark/MHz* Superior performance-per-MHz
2-stage pipeline Compact size for many applications
Static or dynamic branch predication Speed up branch control codes​
Physical Memory Protection (PMP), 16 regions Basic read/write/execute memory protection with minimum cost
Performance monitors Program code performance tuning
StackSafe™ hardware stack protection
  • Easy identification of stack size threshold during development
  • Hardware error detection of stack overflow and underflow at runtime

Multiplier options

  • Fast multiplier: single cycle
  • Small multipliers: multi-cycle
Option to choose between speed and area according to application's requirements

Power Management

  • PowerBrake technology
  • WFI(Wait for Interrupt) and WFE(Wait for Event)
Performance throttling to digitally reduce power consumption WFI instruction and WFE CSR for software power control

* BSP v5.0.0, DMIPS/MHZ without no-inline option, best performances

Memory Subsystems

Key FeaturesBenefits

I-Cache

  • Size: UP to 32KiB
  • Set associativity: Direct-mapped, 2-way 
  • Accelerating accesses to slow memories
  • Flexible cache configurations

I/D Local Memory

  • Size: Up to 512MiB
  • SRAM or AHB-Lite interface support
  • For deterministic and efficient program execution
  • Flexible size selection to fit diversified needs

Bus interfaces

Key FeaturesBenefits

AHB-Lite

  • Synchronous N:1 core-to-bus clock ratio to simplified SoC integration
  • Fast Input/Output (Fast IO)
  • APB
  • User-selectable bus interface for optimal efficiency
  • Fast IO for 0 cycle latency
  • APB interface for private peripherals

Core-Local Interrupt Controller (CLIC)

Key FeaturesBenefits
Up to 1005 interrupt sources, and up to 255 interrupt priority levels Allow core local interrupts to be serviced and prioritized without sharing
Enhanced interrupt features Selective vectoring with priority preemption Support for software-based tail chaining
  • Faster interrupt handling for real-time applications
  • Complete hardware preemption support for faster response
  • Flexible interrupt source interface for simpler SoC design

Platform-Level Interrupt Controller (PLIC)

Key FeaturesBenefits

Implements RISC-V PLIC specification

  • Up to 1023 interrupt sources
  • Up to 255 interrupt priority levels
Interrupt handling for SoC with multiple processors

Enhanced interrupt features

  • Priority-based preemption
  • Selectable edge trigger or level trigger
Complete hardware preemption support

Debug Support

Key FeaturesBenefits
Implements RISC-V debug specifications Supported by industry debug tool suppliers
JTAG Debug Port Industry-standard support
Embedded Debug Module with up to 8 triggers Flexible configurations to tradeoff between gate count and debugging capabilities
Exception redirection support Entering debugger upon selected exceptions without using breakpoints

Performance

Core, ProcessN22, 28HPC+
Frequency (MHz) 50
Dynamic power (uW/MHz) 2.42
Area (mm2) 0.009
Core, ProcessN22, 28HPC+
Frequency (MHz) 700
Dynamic power (uW/MHz) 5.3
Area (mm2) 0.013

* Base configuration, RVT 9-track library, SS corner, 0.81V, -40°C, and with I/O constraint. Power consumption at TT corner, 0.9V, 25°C 

Standard Product Package

  • AndesCore™ N22 with CPU Subsystem
  • Pre-integrated N22, PLIC, Debug Module, and simulation-only encrypted Standard AE250 Platform
  • AndesCore™ N22 with Standard AE250 AHB Platform

FreeStart Product Packages