AndesCore™ AX45MPV

64-bit RISC-V Multicore Processor with 1024-bit Vector Extension

AndesCore™ AX45MPV Overview (Preliminary)

  • 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
  • Symmetric multiprocessing up to 8 cores
  • Level-2 cache and coherence support
  • AndeStar™ V5 Instruction Set Architecture (ISA)
    • Compliant to RISC-V GCBPV extensions
    • Andes performance extension
    • Andes CoDense™ extension for further compaction of code size
  • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
  • 64-bit architecture for memory space over 4GB
  • Branch predication to speed up control code
  • Linux-capable Memory Management Unit (MMU)
  • Physical Memory Protection (PMP) and programmable Physical Memory Attribute (PPMA)
    • Andes-enhanced Platform-Level Interrupt Controller (PLIC) for a wide range of system events and real-time performance
  • Multiprocessing up to 8 cores with hardware managed data coherence
  • Configurable VPU vector length (VLEN) and datapath length (DLEN)
  • Easy arrangement of preemptive interrupts
  • ECC or Parity for SRAM error protection
  • StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
  • Versatile configurations to tradeoff between core size and performance requirements
  • PowerBrake and WFI (Wait For Interrupt) for different power saving occasions

AndesCore™ AX45MPV 64-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture. It supports RISC-V standard “G (IMA-FD)”, “C” 16-bit compression, “B” bit manipulation, DSP/SIMD ‘P’ (draft), “V” (vector) extensions, and Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions. It features MMU for Linux based applications, dynamic branch prediction for efficient branch execution, dual-issue of common instruction pairs, level-1 instruction/data caches and local memories for low-latency accesses. The AX45MPV symmetric multiprocessor supports up to eight cores and a level-2 cache controller with instruction and data prefetch. Coherence Manger ensures data coherence among CPU accesses and IO transactions from cache less bus masters. The AX45MPV contains a powerful VPU with up to 1024-bit VLEN and DLEN, and is excellent for computations involving large arrays of data such as computer vision, cryptography, image processing, machine/deep learning, and scientific computing. Other features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™, StackSafe™ for software quality improvement, PowerBrake and WFI for power management.


  • Computer vision
  • Cryptography
  • Image Processing
  • Machine/Deep learning acceleration
  • Scientific Computing 

Block Diagram

Development Tools

  • AndeSight™ Integrated Development Environment (Eclipse-based)
  • AndeShape™ FPGA Development Boards
  • COPILOT: Automation tool for Andes Customized Extension™
  • AndesClarity™ : Processor Pipeline Analyzer
  • AndeSoft™ NN Library: Optimized for RISC-V DSP/SIMD and Vector extension
  • Debugging Hardware

Product Brief (To be updated)

Key Features and Performance

AndeStar™ V5 (RV64GCBP*V) 64-bit Architecture

Key FeaturesBenefits
RISC-V RV64 GCBP*V (P-ext is in draft)
  • State-of-the art ISA from latest developments in computer architecture
  • Industry standard and open architecture
Andes Extended Instructions Andes exclusive performance and functionality enhancements
MMU and Sv39/Sv48 virtual memory translation For compact code density
16 or 32 general-purpose registers For better code size or performance
Machine (M), optional User (U) and Supervisor (S) Privilege levels Embedded systems with privilege protections

CPU Core

Key FeaturesBenefits
5.64 CoreMark/MHz Superior performance-per-MHz
In order Dual issue, 8-stage pipeline High performance
Enhanced and Supervisor-mode Physical Memory Protection (ePMP and sPMP), each up to 32 entries Enhance core security
Programmable Physical Memory Attributes (PPMA), up to 16 regions Determine read, write, execute permissions of a physical memory region
Performance monitors Program code performance tuning
StackSafe™ hardware stack protection
  • Easy identification of stack size threshold during development
  • Hardware error detection of stack overflow and underflow at runtime

Memory Subsystems

Key FeaturesBenefits

Unified read-only instruction cache, or Instruction and Data Caches

  • Configurable from 8KB up to 64KB
  • Parity for I$; ECC for I$/D$ 
  • Multicore Cache Coherence support up to 8 cores
  • Accelerating accesses to slow memories
  • Flexible cache configurations

I/D Local Memory

  • Size: Individually configurable from 4KB up to 16MB with ECC protection
  • DLM accessible from both scalar and vector core
  • For deterministic and efficient program execution
  • Flexible size selection to fit diversified needs

Bus Interfaces

Key FeaturesBenefits
  • All configurable data width from 128 to 512 bits except 64-bit SSP
  • Memory port for cacheable accesses
  • MMIO port for non-cacheable accesses
  • IOCP (IO Coherence Port) for cache less bus masters
  • System Port with synchronous N:1 core-to-bus clock ratio to provide user-selectable bus interface for optimal efficiency and ease SoC integration
  • Local Memory Access Port allows external bus master to access local memory

Vector Processing Unit (VPU)

Key FeaturesBenefits
  • RISC-V V-extension (RVV) 1.0 spec
  • Custom RVV instructions based on ACE-RVV
  • Standard and Customized RISC-V vector support
  • LMUL supporting 1, 2, 4, 8, 1/2, 1/4, 1/8
  • Configurable VLEN/DLEN from 128 to 1024 bits with 1:1 or 2:1 ratio
  • Multiple independent vector execution units which can execute in parallel
  • Independent memory access paths for RVV load/store and Andes Streaming Port (ASP) load/store
  • Highest performance vector
  • Very Fast Direct memory access to CoProcessor

Platform-Level Interrupt Controller (PLIC)

Key FeaturesBenefits

Implements RISC-V PLIC specification

  • Up to 1023 interrupt sources
  • Up to 255 interrupt priority levels
Interrupt handling for SoC with multiple processors

Enhanced interrupt features

  • Priority-based preemption
  • Selectable edge trigger or level trigger
Complete hardware preemption support

Debug Support

Key FeaturesBenefits
Implements RISC-V debug specifications Supported by industry debug tool suppliers
2-wire serial or 4-wire JTAG Industry-standard support
Embedded Debug Module with 2/4/8 triggers Flexible configurations to tradeoff between gate count and debugging capabilities
Optional password-based secure debug Enhanced secure debugging
RISC-V Trace 1.0 Instruction Trace interface Standard RISC-V trace support


Frequency (MHz) To be updated
To be updated To be updated
Area (mm2) To be updated

Standard Product Package

  • AndesCore™ AX45MPV with AE350 Platform CPU Subsystem
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