General Description
The AE350 AXI/AHB-based platform N25(F)/NX25(F)/D25F/A25/AX25/A27/A27L2/AX27/AX27L2 and 45-series CPU with level-one memories, interrupt controller, debug module, AXI and AHB Bus Matrix Controller, AXI-to-AHB Bridge and a collection of fundamental AHB/APB bus IP components pre-integrated together as a system design. The high-quality and configurable AHB/APB IPs suites a majority embedded systems, and the verified platform serves as a starting point to jump start SoC designs.
Block Diagram
Feature Highlight
Bus Controller / Bridge
- AXI Bus Matrix Controller
- AHB Bus Matrix Controller
- Sync. AXI-to-AHB Bridge
- Async. AXI-to-AHB Bridge
- AHB Bus Decoder
- AHB-to-APB Bridge
- Sync. AXI-to-AHB Bridge
- Async. AXI-to-AHB Bridge
- AHB Bus Decoder
- AHB-to-APB Bridge
APB Bus Components
- DMA Controller (DMAC)
- UART Controller
- Quad Speed SPI Controller
- I2C Controller (IIC)
- GPIO
- Programmable Interval Timer (PIT)/PWM
- Watchdog Timer (WDT)
- Real Time Clock (RTC)
