AndesCore™ A27

Compact High-Speed 32-bit CPU Core with MemBoost and PMA

AndesCore™ A27 Overview

  • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
  • Floating point extensions
  • DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
  • Andes extensions, architected for performance and functionality enhancements
  • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
  • 32-bit, 5-stage pipeline CPU architecture
  • 16/32-bit mixable instruction format for compacting code density
  • Branch predication to speed up control code
  • Return Address Stack (RAS) to speed up procedure returns
  • Memory Management Unit (MMU), Physical Memory Protection (PMP) and Programmable Physical Memory Attributes (PMA)
  • MemBoost for heavy memory transactions
  • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
  • Enhancement of vectored interrupt handling for real-time performance
  • Advanced CoDense™ technology to further reduce code size on top of "C" extension

The 32-bit A27 is a 5-stage processor that supports the latest RISC-V specification, including "G" ("IMAFD") standard instructions, "C" 16-bit compression instructions, "P" Packed-SIMD/DSP instructions, "N" for user-level interrupts, and Memory Management Unit (MMU) for Linux support.

A27 features branch prediction, instruction and data caches, local memories, ECC error protection, and Andes Custom Extension™ to add custom instructions to accelerate performance and reduce power consumption. In addition, it incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. A27 also includes vectored and preemptive interrupt controller to serve diversified system events, AXI 64-bit bus, rich power management, and JTAG debug interface and trace interface for software development support.

Applications

  • Machine/Deep Learning acceleration
  • Networking and Communications
  • Video and Image Processing
  • Advanced Storage Device Control

Block Diagram

Development Tools

  • AndeSight™ Integrated Development Environment
  • COPILOT: Custom-OPtimized Instruction deveLOpment Tool for ACE
  • ICE debugging hardware

Key Features and Performance

AndeStar™ V5 Architecture

Key FeaturesBenefits
RISC-V RV32GC-N-P ISA
  • State-of-the art ISA from latest developments in computer architecture
  • Industry standard and open architecture
RISC-V P-extension (draft) DSP/SIMD instructions with versatile operationsBoost the performance of voice, audio, image and signal processing
RISC-V single and double precision floating point instructionAccelerate the processing of high precision arithmetic
Andes Extended InstructionsAndes exclusive performance and functionality enhancements
Andes Custom Extension™ (ACE) option to create customized instructions for software acceleration
  • Add customized instruction extensions to facilitate Domain-Specific Architecture/Acceleration (DSA)
  • Boost application performance significantly, at the same time maintain the programmability
  • Powerful constructs are available to define high level instruction
  • ACE design is based on Verilog and C languages which are familiar to the designers
  • The COPILOT tool automatically generates the extended CPU and software toolchain
  • Do not require expertise in processor pipeline to design ACE instructions
16/32-bit mixable instruction formatFor compact code density
32 general-purpose registersFor better code size and performance
Machine (M), User (U) and Supervisor (S) Privilege levelsFor Linux and advanced operating systems with protection between kernel and user programs

CPU Core

Key FeaturesBenefits
3.58 Coremark/MHz, 1.96 DMIPS/MHz*Superior performance-per-MHz
5-stage pipeline, with a full-cycle reserved for critical SRAM accessesSuperior performance-efficiency, while allowing for high speeds

Extensive branch predication features

  • Branch Target Buffer (BTB): 32, 64, 128 or 256-entry
  • Branch History Table (BHT): 256-entry, with 8-bit branch history
  • Return Address Stack (RAS): 4-entry
  • Branch Target Buffer and Branch History Table to speed up control codes
  • Return Address Stack to speeds up procedure returns

Memory Management Unit

  • Sv32 virtual-memory systems
  • 4/8-entry fully associative ITLB/DTLB
  • 32/64/128-entry 4-way set-associative shared TLB
  • Hardware page table walker
  • Virtual memory support for full address space and easy code/data sharing
  • Support for full-featured OS such as Linux
  • Protection of supervisor and user privilege
  • Hardware for fast address translation
Physical Memory Protection (PMP), 16 regionsBasic read/write/execute memory protection with minimum cost
Programmable Physical Memory Attribute (PMA), 16 regions

Configurable memory attributes:

  • Memory, I/O, None
  • Cacheable/Non-cacheable
  • Write-back/Write-through
  • Read/write/read & write allocate, no allocate
  • Access fault for non-existent regions
Performance monitorsProgram code performance tuning
StackSafe™ hardware stack protection
  • Easy identification of stack size threshold during development
  • Hardware error detection of stack overflow and underflow at runtime

Multiplier options

  • Fast multiplier: pipelined, 2-cycle
  • Small multipliers: producing 1, 2, 4, or 8 bits per cycle
Option to choose between speed and area according to application's requirements
PowerBrake technologyPerformance throttling to digitally reduce power consumption
QuickNap™ technologyFast power-down/wake-up support for caches

* BSP v5.0.0, DMIPS/MHZ follow Dhrystone's no-inline ground rules, best performances

Memory Subsystems

Key FeaturesBenefits

I-Cache & D-Cache

  • Size: 8KB to 64KB
  • Set associativity: 2-way or 4-way
  • Accelerating accesses to slow memories
  • Flexible cache configurations

ILM & DLM

  • Size: 4KB to 16M
  • SRAM or AHB-Lite interface support
  • Bus masters accesses by AHB slave port
  • For deterministic and efficient program execution
  • Flexible size selection to fit diversified needs
MemBoost – Data Cache Write-AroundSmart cache line allocation policy, for better cache utilization and reduce number of memory accesses
MemBoost – Instruction and Data Pre-fetchConditionally fill instruction and data caches in advance, for minimum memory access latency
MemBoost – Multiple Outstanding Mem. Req.Issue multiple transactions to data memory sub-system for higher bus utilization, also support out-of-order completion
MemBoost – Dedicated I & D Bus InterfacesSeparate instruction and data buses, for instruction and data's own memory transactions
Soft-error protection: ECC or parity for I-Cache and D-Cache, ILM and DLM with SRAM interfaceCode and data integrity protection
Bus master port: AXI with 64-bit data, I/D joint or separate busUser-selectable bus interface for optimal efficiency
Bus save port: AHB with 64-bit data, for ILM/DLM accessesEfficient data transfer between CPU and SoC masters
Core/bus clock ratio of N:1Simplified SoC integration

Platform-Level Interrupt Controller (PLIC)

Key FeaturesBenefits

Implements RISC-V PLIC specification

  • Up to 1023 PLIC interrupt sources
  • Up to 255 PLIC interrupt priority levels
  • Up to 16 PLIC interrupt targets
Allow individual interrupts to be serviced and prioritized without sharing

Enhanced interrupt features

  • Vectored interrupt dispatch
  • Priority-based preemption
  • Selectable edge trigger or level trigger
  • Faster interrupt handling for real-time applications
  • Complete hardware preemption support for faster response
  • Flexible interrupt source interface for simpler SoC design

Debug Support

Key FeaturesBenefits
Implements RISC-V debug specificationsSupported by industry debug tool suppliers
JTAG Debug PortIndustry-standard support
Embedded Debug Module with up to 8 triggersFlexible configurations to tradeoff between gate count and debugging capabilities
Exception redirection supportEntering debugger upon selected exceptions without using breakpoints

Performance

Core, ProcessA27, 28nm
Frequency (MHz)1000
Dynamic power (uW/MHz)21
Area (mm2)0.131

* Configured with 32KB instruction and data caches, MMU with 256-entry BTB, 16-entry PMP and 16-entry PMA, without DSP and FPU. Using SVT 9-track library, SS corner, 0.81V, -40°C, and with I/O constraint. Power consumption at TT corner, 0.9V, 25°C

Product Package

AndesCore™ A27 Single-Core Processor with AE350 Platform

  • Pre-integrated A27 with CPU subsystem (including PLIC, Timer and Debug Module), and AXI platform
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