The wearables market is expected to grow three-fold by 2019, according to research firm CCS Insight when it will ship $25 billion in smart watches, fitness trackers, and wearable cameras. Intel Corp. CFO Stacy Smith stated that battery life is critical in wearable devices and the one feature that’s lacking in wearables, GPS tracking, is a very power-hungry feature. The ultra-low power, very high performance, small silicon footprint AndesCore™ embedded processors are the ideal solution for solving these tough problems facing wearables. For example, AndesCore™ embedded processors have been designed into IoT devices, such as electronic shelf labels, which demand a battery life of more than 5 years.
AndesCore™ embedded processors are based on the AndeStar™ architecture. Designed within the past decade with the needs of emerging IoT devices in mind, the architecture enables enormous power savings while providing high performance. This is achieved through novel functionality such as frequency throttling, patented memory architecture, and custom instructions. Andes PowerBrake™ is a low-cost (few gates) means of achieving CPU frequency throttling without changing the PLL clock. PowerBrake™ allows 16 different performance scales from the highest performance to the lowest, so the processor can throttle up or down to accommodate these different computing requirements.
The major performance and power bottleneck in an IoT device is the flash memory containing its program. Andes FlashFetch™ breaks the bottleneck using a small amount of cache—tiny cache—and a prefetch SRAM buffer. Depending on the CPU frequency, running the Coremark and DMIPS benchmarks with FlashFetch™ can boost the score from 30 to over 100 percent. FlashFetch™ also allows the designer to achieve the same DMIPS performance with a lower clock or maintain the clock and boost the DMIPS performance.
The AndesCore™ capability to add custom instructions to accelerate compute intensive tasks, Andes Custom Extension™ (ACE), may be applied to the thorny problem of incorporating GPS capability in a battery operated device. Custom instructions to accelerate the basic GPS algorithm could provide the performance while reducing power consumption by as much as an order of magnitude. While custom instructions are not new to embedded processors, Andes’ contribution is a powerful tool that greatly eases the task of creating the instructions and incorporating them into the existing software development tools with quick turnaround time. In addition, the ACE logic of the instructions is written in the most popular HDL, Verilog, and is verified against its semantics automatically in the ACE flow.
Only the AndesCore series of high performance 32 & 64-bit CPU cores, designed in the past decade, can deliver the low cost, low power consumption and high performance demanded by today’s emerging high volume wearables applications.