Andes Announces RISC-V Multicore 1024-bit Vector Processor: AX45MPV


Vector Processing is brought to the Award Winning AndesCore™ 45-Series

SAN JOSE, CA – December 7, 2022 – Andes Technology Corporation  (TWSE: 6533; SIN: US03420C2089ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today proudly announces the new member of popular AndesCore™ 45-Series, the AX45MPV with Linux multicore and 1024-bit vector processing capabilities. The AX45MPV targets the applications with large volumes of data such as datacenter AI inference and training, ADAS, AR/VR, computer vision, cryptography, and multimedia.

The AX45MPV inherits all the features of the AX45MP and leverages the 3-year field experience of the successful Andes vector processor NX27V. The AX45MP is a 64-bit 8-stage dual-issue multicore RISC-V processor. It incorporates RISC-V GCBP* extensions, and supports SMP Linux with MMU (Memory Management Unit) and up to 48-bit virtual addresses. In addition, it can be configured to up to eight cores with coherence manager and up to 8MB shared L2 cache memory in a cluster. The coherence manager ensures the data coherence of all L1 data caches and supports the optional IO coherence port. (*P is a draft version)

The Vector Processing Unit (VPU) of the AX45MPV implements RISC-V Vector Extension (RVV) version 1.0. It supports configurations of up to 1024-bit vector width (VLEN) and datapath width (DLEN). The VPU can dual-issue vector instructions to functional units, where instructions with all inputs ready can be executed simultaneously and can produce up to 6 x 1024-bit results every cycle. The data formats can be integer, fixed-point and floating point as well as Andes-extended data types optimized for AI representations. In addition, the vector load and store segment instructions can move multiple contiguous fields in memory to and from consecutive vector registers to allow efficient vector processing of video, audio/speech, complex numbers, and other data. Furthermore, the Andes Streaming Port (ASP), first available in the NX27V, is a dedicated command and data interface to move large amount of data between AX45MPV (scalar and vector) registers and an external accelerator. The command part of the RVV-aware ASP is user-defined with optional on-the-fly operations designed through the powerful Andes Custom Extension™ (ACE) framework.

“The AX45MPV multicore vector processor is another important milestone for Andes and RISC-V enthusiasts since our NX27V, the first RISC-V commercial vector processor and a very successful one announced 3 years ago,” said Andes Chairman and CEO, Frankwell Lin. “Some of our customers are looking for a Linux-capable multicore vector processor with faster data movement and computations. The versatile AX45MPV empowers our customers to fulfill their various demands for compute acceleration. It is exciting to see AX45MPV perfectly satisfy their expectations.”

“Multicore vector processors are designed for applications with high parallelism. The AX45MPV with outstanding scalar performance supports up to eight cores in one cluster with coherence manager and an optional L2 cache controller,” said Dr. Charlie Su, CTO and President of Andes. “Compared with the NX27V at its maximum VPU configuration, 512-bit VLEN and DLEN, the similarly-configured AX45MPV is expected to deliver 20%~40% higher performance for non-MAC dominated computation kernels while the AX45MPV with 1024-bit VLEN and DLEN can deliver 2x performance for MAC dominated kernels. The AX45MPV has being requested by customers whose applications need to process arrays of data with size over 1024 bits.”

The AX45MPV fully supports the AndeStar™ V5 architecture, which includes the latest RISC-V extensions and also Andes extended features such as PowerBrake and QuickNap™ for power saving; StackSafe™ for stack overflow/underflow protection; and CoDense™ for additional code density enhancement on top of RISC-V C-extension. Furthermore, the AX45MPV benefits from all existing Andes development tools for AX45MP and NX27V such as the AndeSight™ IDE and optimizing compilers, the Vector and Neural Network libraries, the intuitive AndesClarity™ pipeline visualizer and analyzer to help optimize performance-critical computation kernels, and Andes Custom Extension™ framework. It can also leverage the broader RISC-V ecosystem from security solutions to system level modeling, and hardware debug/trace subsystems.

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes (TWSE: 6533SIN: US03420C2089ISIN: US03420C1099) is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion since 2021 and continues to rise. In the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion.

For more information, please visit

Follow Andes on TwitterLinkedInYouTube and Facebook.