Andes Webinar 線上開講!

Upcoming Webinar

Important Considerations for Specifying a Main Processor and AI Accelerator


英文場:3/16 (三) 1:00 AM (GMT+8)

Upcoming Webinar

3/16 (三):Important Considerations for Specifying a Main Processor and AI Accelerator

 講者:John Min, Director of Field Application Engineering at Andes Technology
講者:Paul Karazuba, VP of Marketing at Expedera

英文:1:00 AM (GMT+8) → 立即報名 ←  

In specifying the features, functions, and requirements of a main processor and AI accelerator (NPU), system engineers and chip architects often don't consider use cases.

In this webinar, Expedera VP of Marketing Paul Karazuba and Andes Technology Director of Field Applications John Min will examine typical use cases system designers face, and the considerations that should be factored when deciding on main processor and AI accelerator performance requirements.

On-demand Webinar

[Andes x PUFsecurity] Securing the Future with RISC-V

February 25, 2022

講者:John Min, Director of NA Field Application Engineering at Andes Technology & Andrew Irvin, Chairman Office, PUFsecurity | English

While metaverse took the spotlight in recent CES, it is made possible with advancement in computation and connectivity, which also empower many other aspects of people's lives from IoT, Automotive, and to all kinds of applications around us. While Andes RISC-V has continued to make ways into all applications, security in modern SoC design becomes inevitable. In this joint webinar, PUFsecurity and Andes will discuss how to best address security design with Andes RISC-V architecture and share some common pitfalls to avoid.

[Andes Technology]
- Title: Securing the Future - The Essential Solution for RISC-V
- Speaker: John Min, Director of NA Field Application Engineering, Andes Technology

- Title: Securing Andes RISC-V with PUFsecurity
- Speaker: Andrew Irvin, Chairman Office, PUFsecurity

AndeSight™ IDE再升級 進階除錯及系統分析更容易

November 25, 2021

講者:林佳弘 解決方案架構工程處 資深技術經理
AndeSight™ v5.0 提供了完整及強大的軟體開發環境, 包含了全面性的軟體元件以及最佳化的開發工具。
這次我們會介紹 AndeSight™ v5.0的主要進階的除錯功能, 搭配GUI的輔助AndeSight™ 可以提供深入的程式執行狀況。
在Webinar, 我們也會以實際操作的方式, 展示搭配AndeSight™ 的強大外掛程式 AndesClarity™, 它將軟體執行的效能及硬體資源的動態分配情況視覺化, 讓軟體開發者能快速掌控遇到的瓶頸。

次世代向量處理器設計 #4 - 簡化RISC-V 向量擴展記憶體運算

September 30, 2021

講者:Dr. Thang Tran 首席架構師
Dr. Thang Tran, Principal Architect of Andes Technology and veteran of high-performance computing (HPC), on September 30 at 14:00 Taipei Time, for the last in his four-part masterclass series on demystifying the RISC-V Vector Extension.

In this session, Dr. Tran will present a couple of examples using vector instruction vector instructions based on Andes NX27V. He will also discuss NX27V performance, competitive data, tools, and summary.

次世代向量處理器設計 #3 - 揭開RISC-V 向量擴展的秘密

September 1, 2021

講者:Dr. Thang Tran 首席架構師
The hour long event hosted by Andes Technology will be the third of a 4-part lecture series on next-generation vector processor design. It will showcase a 5-stage pipeline and an 8-stage in-order superscalar vector processor based on Andes’ latest AndeStar™ V5 Architecture. Both have design wins at major TSMC foundry customers.

次世代向量處理器設計 #2 - 揭開RISC-V 向量擴展的秘密

August 4, 2021

講者:Dr. Thang Tran 首席架構師
The hour long event hosted by Andes Technology will be the second of a 4-part lecture series on next-generation vector processor design. It will showcase a 5-stage pipeline and an 8-stage in-order superscalar vector processor based on Andes’ latest AndeStar™ V5 Architecture. Both have design wins at major TSMC foundry customers.

次世代向量處理器設計 #1

July 14, 2021

講者:Dr. Thang Tran 首席架構師
Join Dr. Thang Tran, Principal Architect of Andes Technology Corp. and veteran of high-performance computing (HPC), for the first of a 4-part lecture series on next-generation vector processor design. Dr. Tran is an industry expert in HPC development. He architected and designed the Andes RISC-V out-of-order (OOO) Vector Processor (VLEN/SIMD=512b) in 9 months using revolutionary algorithm that does not resemble any previous known OOO superscalar design that has no temporary registers (not renaming, not re-order buffer). The most important feature of this vector processor is simplicity. Andes NX27V issues 8 micro-ops per cycle with up to 14 vector instructions in parallel execution.

Embedded Solutions in IoV

June 1, 2021

講者:林志明  執行長
晶心科技執行長林志明受邀於線上 COMPUTEXFORUM: Future Car主講【Embedded Solutions in IoV】,分享最前端的 電動車、智慧車聯網 及 車用半導體 趨勢發展。
晶心基於適合新興車用科技的 RISC-V 架構推出多款V5 CPU系列,涵蓋入門級、中階32位元及高階64位元核心,包含DSP、FPU、向量、Linux、超純量和多核心等系列。

Andes軟體解決方案加速RISC-V AI與IoT應用開發​

April 28, 2021

講者:王庭昭 技術經理


AndeSysC™-可用於SoC虛擬原型設計且高靈活度RISC-V 中央處理器仿真模型

March 25, 2021

講者:張奕強 市場處技術經理

AndeSysC™ is Andes virtual platform solution based on SystemC to enrich the RISC-V ecosystem. It provides extendable, flexible and near-cycle accurate models of AndesCore™ V5 RISC-V processor IP’s and components for hardware designers to construct SoC prototypes and evaluate and verify their architecture, functionalities and performance before committing to the actual hardware implementation. With virtual models of Andes processors, AndeSight™ IDE and AndeSoft™ software stack, software engineers can jump-start their development on profiling, optimizing, debugging, and testing in parallel to hardware development to accelerate the development cycle of the complex design. 

In this talk, we will provide an overall picture of Andes and RISC-V momentum.  Then we will introduce the concept of the virtual prototyping and AndeSysC™ with a virtual SoC example that fully utilizes the features from AndeSight™ to expedite the development cycle.


Jan 28, 2021

講者:石佳弘 解決方案架構工程處副處長

The SoC industry has seen the fast-growing and diversified demands for a wide range of RISC-V based products: from tiny low-power MCUs for consumer devices, to chips powering enterprise-grade products and datacenter servers; from one power-efficient core to a thousand GHz+ cores working cohesively. To serve the market, Andes has developed a rich portfolio of AndesCore processor IPs already used in the above scenarios. They include compact single-issue cores to feature-rich Linux-capable superscalar cores, cacheless single cores to cache-coherence multicores, and cores capable of processing floating-point and DSP data to those crunching a large volume of vector data. Based on the solid foundation, Andes continues to enrich our product offerings for higher performance efficiency as well as more flexible configurations.

In this talk, we will first give an overview of Andes existing V5 RISC-V processor lineup and present examples of how V5 processors are used in SoC. Then, we will introduce V5 IPs newly added to Andes processor portfolio, the associated software support and their performance data. We will provide an update of Andes Custom Extension™ (ACE) and show how it can further accelerate control and data paths in applications. We will conclude our talk with a summary.

An Introduction to RISC-V Vector Programming with C Intrinsic

Sep 17, 2020

講者:陳枝懋 高級工程師

The "V" ISA extension for vector processing has been proposed to RISC-V to exploit data parallelism in domains such as machine learning and high-performance computing applications. In contrast to traditional SIMD processors with fixed-length vectors, the RISC-V vector extension defines a vector-length agnostic architecture where work is vectorized independently of a vector length that can be discovered at run-time. This is a departure from existing SIMD frameworks where the vector lengths are known statically, and a new intrinsic interface that takes advantage of scalable nature of RISC-V vectors is being developed by the community. This talk will provide an overview of the vector extension and how to program the vector processor, using Andes NX27V as an example, with C-level scalable vector types and intrinsic functions, as well as design choices and future evolution of the API.

RISC-V & SoC Architecture Exploration for AI & ML Many-core Compute Array

Sep 1, 2020

講者:John Min, Director of NA Field Application Engineering | English

This presentation will describe the first RISC-V Processor with Vector extension implemented in TSMC 7nm FF+ process. It will describe the applications adopting RISC-V with demanding real-time and high performance computing as well as machine learning application. The solution to be shown in this presentation has a die area of 0.3mm² and high performance clock speed of 1 GHz.

解決大數據物聯網時代的RISC-V Vector處理器

Aug 13, 2020

講者:王勝雯 客製運算暨技術服務處 處長

RISC-V開放、可客製化的架構開啟了IoT應用的黃金時代,晶心科技RISC-V CPU及向量處理器(Vector Processor)更是高度適用於處理AI、大數據資訊及IoT產品。晶心科技將分享RISC-V International 及其ISA、生態系統之最新發展,並說明晶心科技所提供之產品、服務並分享與客戶共同開發的成功經驗如何以晶心提供RISC-V Vector處理器及Domain-Specific Architectures、ACE等技術,提高客戶SoC產品效能,加速產品上市時程。

Andes Infuses into AI: High-Efficiency and High-Flexibility Processor IPs+NN SDK for AI

Jul 9, 2020

講者:王庭昭 技術經理

To fulfill the diversity of AI applications (e.g., keyword spotting, object detection, etc.) in different environments including edge and cloud, Andes provides you with different choices to fit your AI targets with various requirements (computing power, power consumption, SRAM and code size). In this talk, Andes will introduce how RISC-V Packed-SIMD/DSP processors and RISC-V vector processors provide the high computing efficiency and flexibilities. Further with Andes NN SDK, it will be easy to integrate your AI applications to the shorter time-to-market, and achieve the outstanding utilization of hardware capabilities.


May 21, 2020

講者:紀威宏 市場處副處長

AI、AR / VR、計算機視覺、加解密技術和多媒體處理的應用需要對大量數據進行高速計算。具有強大的RISC-V向量(RVV)擴展指令集和平行執行功能的RISC-V向量處理器可以加快這些應用程式的性能。

AndesCore™ NX27V是第一個支援RISC-V向量指令的商用處理器。NX27V提供向量暫存器(VRF)每個暫存器的大小最大為512位元。它支援RVV標準數據類型,例如整數,定點和浮點,以及為AI優化的Andes增強數據類型。NX27V包含標量(Scalar)單元和向量處理單元(VPU)。VPU具有多個功能單元,每個週期並行操作高達512位元的資料,可支持多樣化應用程式所需的計算吞吐量。為軟體開發的支援,除編譯工具和性能模擬器之外,Andes還為NX27V提供功能強大的圖形化工具,以幫助分析和優化關鍵運算核心的性能。


May 7, 2020

講者:林永正, 資深技術經理


32/64位的45系列為具有8級管線的高效能、超純量RISC-V處理器。45系列的雙發射微架構能一次處理2道指令,因此大幅增加其效能達5.4 Coremark/MHz的世界級水平;且運算速度在28奈米制程下可達1.2GHz。45系列適合用於須要快速反應及高速運算的嵌入式系統,如5G、AI、AR/VR、ADAS、IP surveillance、networking、storage以及V2X等應用。本次研討會將帶您瞭解27及45系列處理器的主要功能,敬請期待!

真無線藍牙耳機(True Wireless Stereo, TWS)解決方案──運用晶心科技D25+ACE的實現

Apr 23, 2020

講者:童偉, 高級工程師

晶心科技的高效率RISC-V D25 CPU支持有DSP/SIMD運算功能的P擴展指令集(P-extension),已被廣泛應用在語音、音訊、影像處理等應用; 此外,D25亦可搭配獨步業界的ACE (Andes Custom Extension™),SoC設計人員只須要撰寫簡易腳本及RTL程式碼,即可自定可用於加速重要的函式,並同時保有低功耗性能的專屬指令集。

而TWS是Bluetooth 5.0的技術應用。隨著數家供應商成功大量出貨,如今在市場非常受歡迎,後續的穩定成長也可預期。此應用的挑戰在於需高速執行多種複雜演算法,同時也需兼顧非常低的功耗要求。本次的網路研討會晶心科技將會介紹基於D25+ACE的高彈性、易整合及低功耗獨特解決方案,一次滿足TWS的高規格需求。這將會是您的最佳TWS方案選擇,敬請期待!


Apr 9, 2020

講者:張奕強 技術經理

隨著從邊緣到雲對特定領域應用的需求大大增加,晶片設計人員需要特別的硬體加速方法來滿足他們的特定需求。奕強將介紹Andes Custom Extension™ (ACE)將高度優化的晶心RISC-V V5內核轉變為特定的應用結構及ACE和COPILOT的主要功能,並共用一些ACE創建自訂指令的示例來加速其軟體執行效能。

晶心科技RISC-V 軟體解決方案

Mar 26, 2020

講者:沈智明 資深技術經理

在開發AndesCore™ CPU的過程中, AndeSight™集合開發環境提供友善的軟件開發介面與調適工具。15年來隨著客戶的回饋與產品的持續進步, AndeSight™已經發展出更全面的功能與穩定的品質。而AndeSoft™ BSP則提供命令列下豐富的軟件項目, 如工具鏈、裸跑範例程式、RTOS/Linux與DSP函式庫相關軟件等。歡迎產業界與學界RISC-V愛好者一同齊聚RISC-V CON線上研討會, 深入了解AndeSight™各個功能組件與AndeSoft™ BSP最新軟件項目。

Andes RISC-V V5 CPUs​

Mar 12, 2020

講者: 賴昱帆 技術經理

Introduction to Andes RISC-V CPU cores lineup, Andes Custom Extensions (ACE), software supports from bare metal to Linux, and Integrated Development Environment (IDE). People who join this webinar will learn what Andes could help designers to create highly competitive domain-specific SoCs easily.

多樣化的RISC-V CON研討會主題

- 晶心 AndesCore™ V5、D25、27系列、45系列處理器核心
- 晶心 RISC-V 向量架構 ( Vector Extension ) 處理器核心
- 晶心處理器客制化擴充功能架構 Andes Custom Extension™
- 智慧物聯網 ( AIoT ) 下多樣化RISC-V應用案例
- 最新 RISC-V市場趨勢及技術
Close Menu