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Upcoming Webinar

Important Considerations for Specifying a Main Processor and AI Accelerator

英文场:3/16 (三) 1:00 AM (GMT+8)

Upcoming Webinar

3/16 (三):Important Considerations for Specifying a Main Processor and AI Accelerator

 讲者:John Min, Director of Field Application Engineering at Andes Technology
讲者: Paul Karazuba, VP of Marketing at Expedera
:00 AM (GMT+8) → 立即报名 ←  

In specifying the features, functions, and requirements of a main processor and AI accelerator (NPU), system engineers and chip architects often don't consider use cases.

In this webinar, Expedera VP of Marketing Paul Karazuba and Andes Technology Director of Field Applications John Min will examine typical use cases system designers face, and the considerations that should be factored when deciding on main processor and AI accelerator performance requirements.

On-demand Webinar

AndeSight™ IDE再升级 进阶除错及系统分析更容易

September 30, 2021

讲者:林佳弘 解决方案架构工程处 资深技术经理

AndeSight™ v5.0 提供了完整及强大的软体开发环境, 包含了全面性的软体元件以及最佳化的开发工具。
这次我们会介绍 AndeSight™ v5.0的主要进阶的除错功能, 搭配GUI的辅助AndeSight™ 可以提供深入的程式执行状况。
在Webinar, 我们也会以实际操作的方式, 展示搭配AndeSight™ 的强大外挂程式 AndesClarity™, 它将软体执行的效能及硬体资源的动态分配情况视觉化, 让软体开发者能快速掌控遇到的瓶颈。

次世代向量处理器设计 #4 - 简化RISC-V矢量扩展存储器运算

September 30, 2021

讲者:Dr. Thang Tran 首席架构师

Dr. Thang Tran, Principal Architect of Andes Technology and veteran of high-performance computing (HPC), on September 30 at 14:00 Taipei Time, for the last in his four-part masterclass series on demystifying the RISC-V Vector Extension.

In this session, Dr. Tran will present a couple of examples using vector instruction vector instructions based on Andes NX27V. He will also discuss NX27V performance, competitive data, tools, and summary.

次世代矢量处理器设计 #3 - 揭开 RISC-V 矢量扩展的秘密

September 1, 2021

讲者:Dr. Thang Tran 首席架构师

The hour long event hosted by Andes Technology will be the third of a 4-part lecture series on next-generation vector processor design. It will showcase a 5-stage pipeline and an 8-stage in-order superscalar vector processor based on Andes’ latest AndeStar™ V5 Architecture. Both have design wins at major TSMC foundry customers.

次世代矢量处理器设计 #2 - 揭开 RISC-V 矢量扩展的秘密

August 4, 2021

讲者:Dr. Thang Tran 首席架构师

The hour long event hosted by Andes Technology will be the second of a 4-part lecture series on next-generation vector processor design. It will showcase a 5-stage pipeline and an 8-stage in-order superscalar vector processor based on Andes’ latest AndeStar™ V5 Architecture. Both have design wins at major TSMC foundry customers.

次世代矢量处理器设计 #1

July 14, 2021

讲者:Dr. Thang Tran 首席架构师

Join Dr. Thang Tran, Principal Architect of Andes Technology Corp. and veteran of high-performance computing (HPC), for the first of a 4-part lecture series on next-generation vector processor design. Dr. Tran is an industry expert in HPC development. He architected and designed the Andes RISC-V out-of-order (OOO) Vector Processor (VLEN/SIMD=512b) in 9 months using revolutionary algorithm that does not resemble any previous known OOO superscalar design that has no temporary registers (not renaming, not re-order buffer). The most important feature of this vector processor is simplicity. Andes NX27V issues 8 micro-ops per cycle with up to 14 vector instructions in parallel execution.

Andes软体解决方案加速RISC-V AI与IoT应用开发​

April 28, 2021

讲者:王庭昭 技术经理


AndeSysC™-可用于SoC虚拟原型设计且高灵活度RISC-V 中央处理器仿真模型

Mar 25, 2021

讲者:张奕强 市场处技术经理

AndeSysC™ is Andes virtual platform solution based on SystemC to enrich the RISC-V ecosystem. It provides extendable, flexible and near-cycle accurate models of AndesCore™ V5 RISC-V processor IP’s and components for hardware designers to construct SoC prototypes and evaluate and verify their architecture, functionalities and performance before committing to the actual hardware implementation. With virtual models of Andes processors, AndeSight™ IDE and AndeSoft™ software stack, software engineers can jump-start their development on profiling, optimizing, debugging, and testing in parallel to hardware development to accelerate the development cycle of the complex design. 

In this talk, we will provide an overall picture of Andes and RISC-V momentum.  Then we will introduce the concept of the virtual prototyping and AndeSysC™ with a virtual SoC example that fully utilizes the features from AndeSight™ to expedite the development cycle.


Jan 28, 2021

讲者:石佳弘 解决方案架构工程处副处长

The SoC industry has seen the fast-growing and diversified demands for a wide range of RISC-V based products: from tiny low-power MCUs for consumer devices, to chips powering enterprise-grade products and datacenter servers; from one power-efficient core to a thousand GHz+ cores working cohesively. To serve the market, Andes has developed a rich portfolio of AndesCore processor IPs already used in the above scenarios. They include compact single-issue cores to feature-rich Linux-capable superscalar cores, cacheless single cores to cache-coherence multicores, and cores capable of processing floating-point and DSP data to those crunching a large volume of vector data. Based on the solid foundation, Andes continues to enrich our product offerings for higher performance efficiency as well as more flexible configurations.

In this talk, we will first give an overview of Andes existing V5 RISC-V processor lineup and present examples of how V5 processors are used in SoC. Then, we will introduce V5 IPs newly added to Andes processor portfolio, the associated software support and their performance data. We will provide an update of Andes Custom Extension™ (ACE) and show how it can further accelerate control and data paths in applications. We will conclude our talk with a summary.

An Introduction to RISC-V Vector Programming with C Intrinsic

Sep 17, 2020

讲者:陈枝懋 高级工程师

The “V” ISA extension for vector processing has been proposed to RISC-V to exploit data parallelism in domains such as machine learning and high-performance computing applications. In contrast to traditional SIMD processors with fixed-length vectors, the RISC-V vector extension defines a vector-length agnostic architecture where work is vectorized independently of a vector length that can be discovered at run-time. This is a departure from existing SIMD frameworks where the vector lengths are known statically, and a new intrinsic interface that takes advantage of scalable nature of RISC-V vectors is being developed by the community. This talk will provide an overview of the vector extension and how to program the vector processor, using Andes NX27V as an example, with C-level scalable vector types and intrinsic functions, as well as design choices and future evolution of the API.

RISC-V & SoC Architecture Exploration for AI & ML Many-core Compute Array


讲者:John Min, Director of NA Field Application Engineering | English

This presentation will describe the first RISC-V Processor with Vector extension implemented in TSMC 7nm FF+ process. It will describe the applications adopting RISC-V with demanding real-time and high performance computing as well as machine learning application. The solution to be shown in this presentation has a die area of 0.3mm² and high performance clock speed of 1 GHz.

解决大数据物联网时代的 RISC-V Vector处理器


讲者:王胜雯 客制运算部处长

RISC-V开放、可客制化的架构开启了IoT应用的黄金时代,晶心科技RISC-V CPU及向量处理器(Vector Processor)更是高度适用于处理AI、大数据信息及IoT产品。晶心科技将分享RISC-V International 及其ISA、生态系统之最新发展,并说明晶心科技所提供之产品、服务并分享与客户共同开发的成功经验如何以晶心提供RISC-V Vector处理器及Domain-Specific Architectures、ACE等技术,提高客户SoC产品效能,加速产品上市时程。

Andes Infuses into AI: High-Efficiency and High-Flexibility Processor IPs+NN SDK for AI


讲者:王庭昭 技术経理

To fulfill the diversity of AI applications (e.g., keyword spotting, object detection, etc.) in different environments including edge and cloud, Andes provides you with different choices to fit your AI targets with various requirements (computing power, power consumption, SRAM and code size). In this talk, Andes will introduce how RISC-V Packed-SIMD/DSP processors and RISC-V vector processors provide the high computing efficiency and flexibilities. Further with Andes NN SDK, it will be easy to integrate your AI applications to the shorter time-to-market, and achieve the outstanding utilization of hardware capabilities.



讲者:纪威宏 市场处副处长

AI、AR / VR、计算器视觉、加解密技术和多媒体处理的应用需要对大量数据进行高速计算。具有强大的RISC-V向量(RVV)扩展指令集和平行执行功能的RISC-V向量处理器可以加快这些应用程序的性能。

AndesCore™ NX27V是第一个支援RISC-V向量指令的商用处理器。NX27V提供向量缓存器(VRF)每个缓存器的大小最大为512位。它支援RVV标准数据类型,例如整数,定点和浮点,以及为AI优化的Andes增强数据类型。NX27V包含标量(Scalar)单元和向量处理单元(VPU)。VPU具有多个功能单元,每个周期并行操作高达512位的数据,可支持多样化应用程序所需的计算吞吐量。为软件开发的支持,除编译工具和性能仿真器之外,Andes还为NX27V提供功能强大的图形化工具,以帮助分析和优化关键运算核心的性能。



讲者:林永正 资深技术経理


32/64位的45系列为具有8级管线的高效能、超纯量RISC-V处理器。45系列的双发射微架构能一次处理2道指令,因此大幅增加其效能达5.4 Coremark/MHz的世界级水平;且指令周期在28奈米制程下可达1.2GHz。45系列适合用于须要快速反应及高速运算的嵌入式系统,如5G、AI、AR/VR、ADAS、IP surveillance、networking、storage以及V2X等应用。

AR/VR、ADAS、IP surveillance、networking、storage以及V2X等應用。本次研討會將帶您瞭解27及45系列處理器的主要功能,敬請期待!


真无线蓝牙耳机(True Wireless Stereo, TWS)解决方案 -- 运用晶心科技D25+ACE的实现


讲者:童伟 高级工程师 

晶心科技的高效率RISC-V D25 CPU支持有DSP/SIMD运算功能的P扩展指令集(P-extension),已被广泛应用在语音、音频、图像处理等应用此外,D25亦可搭配独步业界的ACE (Andes Custom Extension)SoC设计人员只须要撰写简易脚本及RTL程序代码,即可自定可用于加速重要的函式,并同时保有低功耗性能的专属指令集。

TWSBluetooth 5.0的技术应用。随着数家供货商成功大量出货,如今在市场非常受欢迎,后续的稳定成长也可预期。此应用的挑战在于需高速执行多种复杂算法,同时也需兼顾非常低的功耗要求。本次的网络研讨会晶心科技将会介绍基于D25+ACE的高弹性、易整合及低功耗独特解决方案,一次满足TWS的高规格需求。这将会是您的最佳TWS方案选择敬请期待



讲者:张奕強 技术経理

随着从边缘到云对特定领域应用的需求大大增加,芯片设计人员需要特别的硬件加速方法来满足他们的特定需求。奕强将介绍Andes Custom Extension™ (ACE)将高度优化的晶心RISC-V V5内核转变为特定的应用结构及ACE和COPILOT的主要功能,并共享一些ACE创建自定义指令的示例来加速其软件执行效能。

晶心科技RISC-V 软件解決方案


讲者:沈智明 资深技术経理

在开发AndesCore™ CPU的过程中, AndeSight™集合开发环境提供友善的软件开发接口与调适工具。15年来随着客户的回馈与产品的持续进步, AndeSight™已经发展出更全面的功能与稳定的质量。而AndeSoft™ BSP则提供命令行下丰富的软件项目, 如工具链、裸跑范例程序、RTOS/Linux与DSP函式库相关软件等。

欢迎产业界与学界RISC-V爱好者一同齐聚3月26日下午两点的RISC-V CON在线研讨会, 深入了解AndeSight™各个功能组件与AndeSoft™ BSP最新软件项目。

Andes RISC-V V5 CPUs​


讲者:童伟 高级工程师

Introduction to Andes RISC-V CPU cores lineup, Andes Custom Extensions (ACE), software supports from bare metal to Linux, and Integrated Development Environment (IDE). People who join this webinar will learn what Andes could help designers to create highly competitive domain-specific SoCs easily.

多样化的RISC-V CON研讨会主题

- 晶心 AndesCore™ V5、D25、27系列、45系列处理器核心
- 晶心 RISC-V 向量架构 ( Vector Extension ) 处理器核心
- 晶心处理器客制化扩充功能架构 Andes Custom Extension™
- 智能物联网 ( AIoT ) 下多样化RISC-V应用案例
- 最新 RISC-V市场趋势及技术
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