Andes Targets Sensor SoCs with its Ultra Power-Efficient Processor Core

【Taiwan HsinChu】“The total number of sensor units is estimated to grow from just under 10 billion in 2012 to nearly 30 billion in 2017,” said Tony Massimini, chief of technology at Semico Research. Noticing the soaring trend of sensor-based applications, Andes Technology Corporation, the first dedicated vendor of innovative 32-bit CPU IPs and associated SoC platforms in Asia, drives its ultra energy-efficient, cost-effective 32-bit processor AndesCore™ N705 to the emerging market. Announced last April in Andes-Embedded Forum, the N705 is an achievement of Andes’ 8-years research. It delivers 141 DMIPS/mw at 90nm low power process, which outperforms competing products from other industry-leading vendors by 30%. Code named “Hummingbird,” the N705 is geared towards light-weight and low-power products. Featuring ultra power-efficiency, compact gate count and the exclusive FlashFetch™ technology, the N705 caters to all sorts of sensor-based applications including smart sensors and sensor hubs.

The N705 provides Instruction/Data Local Memory interface option that allows direct connection to memory. In addition to AHB-lite, it directly incorporates APB bus interface for lower-speed devices. These characteristics effectively reduce the cost of sensor SoCs, speed the development and integration flow, and enable faster time-to-market. While applications like the IoT (Internet of Things), automobiles, and mobile devices are demanding more abilities to capture and interpret environmental conditions (pressure, temperature, motion, proximity and more), the N705 with the built-in 32-bit multiplier and divider accelerates the complex calculation required for sensor fusion algorithm. Using the latest AndeStar™ V3m architecture, it also significantly reduces code size.

The AndesCore N705 is a 32-bit general purpose embedded processor that demonstrates extreme power-efficiency. For ease of integration in SoC design, it is delivered with a reference design flow to meet diversified requirements in performance, power consumption and die area. In addition, it also comes with a complete software development package including the all-C Embedded Programming environment, C libraries optimized for MCUs and 2-wire low-cost ICE debugger. In its minimum configuration, the N705 achieves the leading-edge energy efficiency of 141 DMIPS/mWatt at the 90nm low power process with only 12K gates. Reaching up to 1.51 DMIPS/MHz and 2.62 CoreMark/MHz, the N705 stands out among 32-bit embedded CPUs of the similar complexity.

Jyh-Ming Frankwell Lin, President of Andes Technology Corporation, said, “As sensors are getting ubiquitous, applications in this era must have a compact size and deliver high performance with low power consumption. The AndesCore N705 offers competitive power-efficiency, low gate count and rich interfaces, making it ideal for the design of sensor fusion SoCs. Moreover, it can be connected to the low-speed and power-hungry flash memory directly. Utilizing the FlashFetch™ technology, the N705 is capable to run at its full speed without being hindered by the flash memory and meanwhile reduces over 50% flash power consumption in EEMBC’s CoreMark® benchmark. By all means the optimal choice for developers, the N705 together with the comprehensive software support is ready to take sensor-based applications to the next level.”

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The 9th Andes-Embedded Forum (AEF-9) Takes Place in Hsinchu and Shanghai

Andes Technology Corporation’s 9th Embedded Forum (AEF-9) focusing on IoT and Wearable Solution was successfully held in Hsinchu, Taiwan on May 22 and in Shanghai, China on May 29. Andes President Frankwell Lin gave a keynote speech about Andes’ achievements and progress over the past whole year and expressed deep appreciation to Andes’ partners and customers for their support. Dan Kochpatcharin, Deputy Director of IP Portfolio Marketing at TSMC, also gave a speech on “Smart Connected Life” for the opening. A series of speeches surrounding IoT and Wearables followed then successively to demonstrates Andes’ strength for the emerging IoT/Wearable era. These speeches included “IoT and Wearable Applications Evolution and Outlook,” “Extending Beyond Today’s Performance Horizon Through Andes Customer Extension™,” “Building Low-Power SoC for IoT and Wearable Computing Through Andes Processor/Platform Solutions,” “Andes Software Solutions for Smart Connected Devices,” “32-bit MCU for NFC Reader Applications,” “Development of Smart Wearable Devices” and “Relationship between CES 2014 and Andes Service.” Together with the Q&A session and Andes’ partner/customer exhibitions, the AEF-9 enabled participants to share techniques and exchange experiences in shaping the IoT/Wearable world.

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Andes Wins Over Large Publicly Traded Company as Newcomer to Japanese Market

【Taiwan HsinChu】Even with the slow recovery of global economy in 2013, the demand of semiconductor business in Japan is projected to see a healthy growth of 5.8% to reach $43.4 billion, according to a report from Industry & Technology Intelligence Service (ITIS). Playing a significant role in the semiconductor industry, Japan is a target market that Andes Technology won’t miss when considering going global. After steady efforts to promote AndesCore™, Andes scored its first win in Japan this August by licensing N705-S to a vendor of electrical/electronic equipments. The licensee is a large Japanese publicly traded company with annual revenue of over $2 billion and focuses on the production of temperature controllers, flow control instruments and heat treatment controllers. Andes stands out among competitors, including the one with the largest CPU IP market share, for the superiority of AndesCore™ CPUs in terms of power, performance, and area (PPA). In addition, the licensee is impressed with Andes’ comprehensive development tools and RTOS support. Furthermore, Andes offers prompt and efficient customer support that fully matches high quality standards of the Japanese company.

Andes has started expanding its business to Japan since last year. Its brand yet remains relatively unknown in the country, despite the good reputation and market share in Taiwan, China and Korea. Therefore, in addition to signing contract with the large publicly traded company, Andes also undertakes several marketing activities in Japan. Recent ones are the participation in GSA Semiconductor Leader Forum (Tokyo, October 29th) and Embedded Technology Conferences & Exhibition (Yokohama, November 20th). Through these activities, Andes expects to create awareness of Andes CPU cores and generate more customers in Japan.

Jyh-Ming Frankwell Lin, President of Andes Technology Corporation, stated, “To provide potential customers in Japan with a variety of choices, in the short term, Andes plans to introduce higher-end processors, such as N9, N10 and N13, along with the promotion of N705-S. While Andes also enters the final evaluation stage of another Japanese company now, we believe that our strengths in ultra low power through performance efficiency, small die size and solutions to address SoC issues will be recognized by more and more companies here. In the long run, Andes will reinforce ties with customers by attending international conferences and organizing forums. An upcoming in-depth book about Andes CPU cores by Munetomo Maruyama (32-Bit CPU Core Developed in Taiwan: AndesCore, CQ publishing) is also expected to seize the interests of electrical/electronic system manufacturers, IC design houses and IDMs in Japan. We look forward to the rapid growth of Andes licensees here in the near future.”For more information about Andes Technology and AndesCore™, Andes high-performance/low-power 32-bit processor cores, please referto www.andestech.com or contact sales@andestech.com.

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Andes Exhibits at TSMC 2014 NA Technology Symposium Ecosystem Pavilion

Andes Technology exhibited at the TSMC 2014 NA Technology Symposium Ecosystem Pavilion, San Jose McEnery Convention Center, California, on April 22. Participating with other TSMC OIP (Open Innovation Platform) ecosystem member companies, Andes as an IP partner introduced its high performance, low power 32-bit processor core families with SoC development environment to attendees and showcased AndesCore™-embedded applications which have been in mass production. In the exhibition, booth visitors were impressed with Andes’ competitive CPU IPs and robust platform solutions while exchanging information with Andes US staff. Andes also demonstrated in the event that it’s ready to get deeper and broader involvement in the design ecosystem with its most advanced CPU IP technology.
 

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Andes Technology Launched AndeStar™ V3

 a New-Generation Smart Low-Power 16-/32-bit Mixable Instruction Set Architecture (ISA), to Reduce IC Cost, Improve Efficiency, Facilitate Development and Shorten Time-to-Market 

【Taiwan HsinChu】For years, Andes Technology has been dedicated to developing CPUs and platforms that deliver easy integration, scalability, and design flexibility. To cater to demands of IC design companies and OEMs, it also offers comprehensive product lines and feature-rich development tools. Recently in its 7th Andes-Embedded™ Forum, Andes Technology announced the launch of AndeStar™ V3, a new-generation, smart, low-power Instruction Set Architecture (ISA). AndeStar™ V3 is 16-/32-bit mixable ISA and backward-compatible to V2 ISA. It minimizes executable code size to allow customers to adopt smaller-sized memory to reduce IC cost or put more features in the same-sized memory. In terms of MCU benchmarks, AndeStar™ V3 demonstrates executable code size reduction of over 20% on average when the size of the V3 code is compared to that of the preceding V2 code. With the introduction of All-C Embedded Programming development environment, AndeStar™ V3 enhances the performance of interrupt handlers and improves debugging capabilities, thereby significantly shortening product development cycle and time-to-market for customers.

The applications of AndeStar™ V3 are extensive, including networking, DTV, Digital Home, DSC, DVD, game consoles, PC peripherals, storage, smart meters, industrial control, automobiles, medical devices, and various communication protocols such as Bluetooth and WiFi. AndeStar™ V3’s features and functionalities serve to raise the competitiveness of these product applications in the global market.  

Dr. Chuan-hua Chang, Director of Architecture Division at Andes, stated, “V3-based CPUs can run V2’s executable code as AndeStar™ V3 is backward-compatible. After upgrading their CPU cores to V3-based CPUs, existing V2-based CPU customers do not have to modify or recompile their programs in a hurry. However, they can benefit fully from the features of V3 ISA by recompiling their programs. The V3 program development toolchain will use special instructions to reduce repeated instructions, replace frequently-used instruction sequences with fewer instructions, and use shorter instructions to handle common tasks of functions. These features all bring effective boosts to code density.”
Dr. Chuan-hua Chang further explained, “AndeStar™ V3 offers compiler support for hardware architecture. That is, it provides a development environment of All-C Embedded Programming for developers to write all their code in C and save the trouble of using assembly language. As to interrupt service routines, AndeStar™ V3 adopts priority-based preemptive interrupt scheme. CPU will handle an interrupt request with the highest priority first, thus speeding up the handling of higher priority interrupts and increasing overall efficiency. Moreover, AndeStar™ V3 also improves debugging capabilities, enabling early discovery of problems that are not very obvious. – With all these features, AndeStar™ V3 not only accelerates time-to-market but also greatly reduces development time, revision, and maintenance overhead.”

Please contact sales@andestech.com for more information about AndeStar™ V3, the new-generation smart low-power backward-compatible 16-/32-bit mixable Instruction Set Architecture.

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Andes Technology Launched AndesCore™ SN801, the New Generation Processor Core with Security Features.

With High Power-Efficiency and Side Channel Attack Prevention, SN801 Becomes the Best Choice for SoC Developers when Designing Lightweight and Low-power Secure Products.
 

【Taiwan HsinChu】For new-generation SoC design, delivering 32-bit features and performance along with 8/16-bit cost is a must if one wants to stand out in a competitive market. To meet these requirements, Andes Technology launched the latest-generation AndesCore™ SN801, a 32-bit CPU with advanced security features, in its recent 7th Andes-Embedded™ Forum. SN801 is based on the energy-efficient N801 processor core and designed with secure MPU (Memory Protection Unit). It not only adopts a comprehensive protocol to manage privilege levels but also provides hardware mechanisms for code and data protection. Effectively preventing side channel attacks, AndesCore™ SN801 processor core is the best choice for SoC developers to design lightweight and low-power secure products.

AndesCore™ SN8 series combines streamlined 3-stage pipeline with protective instruction set architecture. With its complete and robust architecture, SN801 enables customers to assign security levels by setting passwords or implement tamper-proof mechanisms according to application needs. The applications of SN801 cover from emerging NFC, bank cards, medical insurance cards, memory cards to e-passports and more. By migrating to SN801 that significantly surpasses legacy 8/16-bit processors, IC design companies can hammer out low-cost, low-power, highly secure and competitive products to address ever-renewing and fast-growing applications.

Dr. Charlie Su, Chief Technical Officer and VP of R&D at Andes, states, “According to a market research report, the global shipments of smart cards are expected to reach around 8.5 billion units by 2013. Specifically targeting applications pertaining to smart cards, AndesCore™ SN801 accelerates the associated SoC design and development, reduces the time for product certification and speeds the entry to market, thereby benefiting customers to vie for share of the ten-billion-unit smart card market. AndesCore™ SN801 fully caters to the demand of new generation SoC design with its 32-bit features and 8/16-bit cost advantage, making it the optimal choice for SoC developers when designing lightweight and low-power secure products.”    For more information about the embedded AndesCore™ SN8 series, please refer to www.andestech.com or contact sales@andestech.com

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Andes Leads The Industry by Reducing Power Consumption for New Embedded Devices New Lower-Power Processor Solutions for Wearable Computing, IOT and other Power-Critical Applications

【Santa Clara, CA, October 2, 2013】 – Andes Technology (www.andestech.com), Asia’s leading supplier of licensable processor cores, today disclosed plans for a new class of ultra-low power processor core solutions.  These products will incorporate a new technology called FlashFetch™ as well as other energy reducing innovations.  Collectively, these new capabilities are designed to meet the most demanding, power-sensitive requirements for applications such as Wearable Computing devices, IoT (Internet of Things) and other flash-memory based requirements.  Building upon Andes’ successful line of performance-efficient IP cores, already in hundreds of millions of products, the company is breaking new ground by further reducing energy consumption and extending battery life to enable a new class of devices.

Speaking from TSMC’s Open Innovation Platform(OIP) ecosystem conference, Andes’ President, Frankwell Lin, explained: “Reducing energy consumption is a global need and we are committed to help that through innovations in performance-efficiency.  These new products enable our customers to rebalance performance and power consumption, resulting in SOCs that consume less energy to accomplish their work.  This helps extend battery life for the next generation of embedded devices – like the new Wearable Computing products that are starting to emerge.”  Andes is demonstrating their entire product line at their booth at the OIP conference.

Andes new low power solutions have impact beyond the processor cores.  The techniques used allow lower speed memories to be used, saving power without sacrificing performance and also enable the creation of off-core program buffers.  Moreover, modeling application performance of is simplified with the AndesSight™ development environment.  This allows customers to experiment with alternate hardware approaches to optimize power, performance and size for their specific software.

“As the new class of SoC solutions for IoT applications becomes better defined, one trend that is emerging is the need for very low power consumption and high power efficiency in the silicon,” said Rich Wawrzyniak, Sr. market Analyst at Semico Research. “Approaches and products that allow designers to realize good performance while delivering power efficiency will be well-received in the market and enjoy a large degree of success.” Wawrzyniak went on to say, “the research Semico is doing today on IoT applications shows the potential for very large unit volumes in the near future to support IoT implementations in both consumer and commercial environments. Good solutions in one area have the potential of being adopted in other areas of the market and the Andes Technology use of the FlashFetch technology can impact silicon solutions aimed at these other market segments. This design solution can have a synergistic effect on Andes’ growth into these newer market segments.”

These new low power solutions featuring FlashFetch, COPILOT, PowerBrake and other new techniques will be discussed at the upcoming Linley Tech Processor Conference on October 16th and 17th at Hyatt Regency, Santa Clara. 

For more information about the AndesCore™ N7 Series, FlashFetch or any of our other low-power, high-performance IP cores and subsystems, please refer to www.andestech.com or contact us at america@andestech.com

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Andes Embedded Processor Symposium 2013 Held in Korea

Co-organized by Andes and KIPEX, Andes Embedded Processor Symposium 2013 was held on Sep 12, 2013 at EL Tower, Seoul, Korea. Specially designed for embedded SoC designers and ASIC design service companies, speeches focused on Andes high performance, low power 32-bit processors and the associated SoC development platforms. Attendees were introduced to new-generation SoC solutions that meet rapidly-growing demands on better scalability, flexibility, performance, cost and power saving.

In the symposium, Andes Sales VP presented three major trends of device creation, the evolution of embedded CPUs and the MCU market analysis; Andes FAE Director introduced Andes advantages in hardware for MCU applications and Linux applications; Andes Sr. Technical Manger introduced Andes proprietary instruction set architecture AndeStar™, Andes software development environment AndeSight™ and complier optimization.

The symposium will be held periodically in the future. Through the event, Andes plans to bring the first hand technology development to the Korean industry and enhance interaction with customers there.

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Andes Launches AndeSight™ v2.0.0 STD Edition, Offering SoC Developers a Sophisticated Development Suite to Ｍeet Diverse Requirement

【Taiwan HsinChu】 Andes Technology, the dedicated vendor of 32-bit CPU IP and associated SoC platforms, launches the AndeSight v2.0.0 STD Development Suite tailored for middle- and high-end market after the rollout of its MCU version for low-end market. AndeSight v2.0.0 STD is characterized by its brand new GUI layout based on Eclipse CDT 8.0 and customization features Chip Profile, Flash ISP and Plugin API with excellent integrity. In addition to the existing AndesCore™ processor cores, AndeSight v2.0.0 STD extends its supports to the newest member, N1337, and cooperates with the Andes ICE solutions, AndeShape™ AICE and AICE-MCU. With these features, AndeSight v2.0.0 STD has become a sophisticated development tool that can catch up with the future trend and meet diverse requirements. 

AndeSight v2.0.0 STD not only includes functions in the MCU version but also enhances its functionalities for setting up the development environment, debugging and verification. Integrating with Andes ESL Integrated Virtual Environment AndESLive™, AndeSight v2.0.0 STD comes with virtual evaluation platform Simulator and graphical interface SoC Builder that enables the construction of virtual SoCs. In terms of debugging, it provides two configurations specific for Linux target environment – Linux Application debugging and Attach to Process debugging. 

AndeSight v2.0.0 STD also offers various functions to customize development environment, including Chip Profile, Flash Burner and Plugin API. Chip Profile contains project templates for specific targets, preventing developers from repetitive configuration for the same targets. As to Flash Burner, users can modify the sample Flash Driver to meet their own flash type and perform pertinent flash programming through the built-in Flash ISP graphical interface. Plugin API allows users to utilize the resources of AndeSight with their own plugin programs. The graphical interface Chip Profile Editor facilitates developers to quickly configure Chip Profile components for individual SoCs. A Chip Profile can be generated by simply configuring the parameters of Chip Profile components, such as project template, Flash Driver, SoC Registers, and Memory Map.

The toolchains of AndeSight v2.0.0 STD support existing CPU N7, N8, SN8, N9, N10 and also N13, the newest member of AndesCore family. Supported by AndeStar™ V3/V3m ISA, the toolchains enable a development environment of All-C Embedded Programming. Programmers can produce high quality code efficiently by writing all their code in C and save the trouble of using assembly language. On the side of RTOS support, AndeSight v2.0.0 STD provides RTOS Awareness feature for μC/OS-II and FreeRTOS, rendering developers visualized high-level debugging for RTOS applications. 

With regard to the debugging solutions, AndeSight v2.0.0 STD can work with both AndeShape AICE and AICE-MCU. The former has been enhanced to deliver better functionality and efficiency; the later supports two-wire JTAG interface so that users can be benefited from reduced pin counts and SoC cost. AndeShape AICE-MCU supports the Debug-on-Reset and Secure Access features in addition to AndesCore’s standard debugging mechanisms such as hardware breakpoint and step-over. It also provides auto frequency calibration and effective download speed, offering customers a low cost niche while maintaining high compatibility with development environment.  

Based on AndeSight v2.0.0 MCU, the newly-launched STD version has a significant upgrade on efficiency and stability. It allows SoC engineers to develop programs on virtual SoC platforms and perform verification on real boards. It also provides advanced debugging utilities to ease the development process and various startup demo programs to get users acquainted with hardware/software environment in less time. 

Dr. Charlie Su, Chief Technical Officer and VP of R&D at Andes, states, “To Andes, introducing high quality and efficient development tools are just as important as launching leading embedded CPU IP AndesCores. We expect AndeSight to be easy-to-use, deliver higher efficiency with optimized code and provide extensive supports for hardware, software and system. The new features of AndeSight v2.0.0 STD are derived from customers’ feedbacks, numerous internal discussion and revisions. Its performance, new functionalities and customization features Chip Profile Editor and Plugin API demonstrate Andes’ continuous efforts on software enhancement and fulfill our commitments to the customers. We look forward to seeing our customer Seize Today’s Dreams and Shape Tomorrow’s Devices with AndeSight v2.0.0 STD.”

For more information about AndeSight v2.0.0 STD Edition and AndeShape AICE-MCU, please refer to www.andestech.com or contact sales@andestech.com

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