a New-Generation Smart Low-Power 16-/32-bit Mixable Instruction Set Architecture (ISA), to Reduce IC Cost, Improve Efficiency, Facilitate Development and Shorten Time-to-Market
【Taiwan HsinChu】For years, Andes Technology has been dedicated to developing CPUs and platforms that deliver easy integration, scalability, and design flexibility. To cater to demands of IC design companies and OEMs, it also offers comprehensive product lines and feature-rich development tools. Recently in its 7th Andes-Embedded™ Forum, Andes Technology announced the launch of AndeStar™ V3, a new-generation, smart, low-power Instruction Set Architecture (ISA). AndeStar™ V3 is 16-/32-bit mixable ISA and backward-compatible to V2 ISA. It minimizes executable code size to allow customers to adopt smaller-sized memory to reduce IC cost or put more features in the same-sized memory. In terms of MCU benchmarks, AndeStar™ V3 demonstrates executable code size reduction of over 20% on average when the size of the V3 code is compared to that of the preceding V2 code. With the introduction of All-C Embedded Programming development environment, AndeStar™ V3 enhances the performance of interrupt handlers and improves debugging capabilities, thereby significantly shortening product development cycle and time-to-market for customers.
The applications of AndeStar™ V3 are extensive, including networking, DTV, Digital Home, DSC, DVD, game consoles, PC peripherals, storage, smart meters, industrial control, automobiles, medical devices, and various communication protocols such as Bluetooth and WiFi. AndeStar™ V3’s features and functionalities serve to raise the competitiveness of these product applications in the global market.
Dr. Chuan-hua Chang, Director of Architecture Division at Andes, stated, “V3-based CPUs can run V2’s executable code as AndeStar™ V3 is backward-compatible. After upgrading their CPU cores to V3-based CPUs, existing V2-based CPU customers do not have to modify or recompile their programs in a hurry. However, they can benefit fully from the features of V3 ISA by recompiling their programs. The V3 program development toolchain will use special instructions to reduce repeated instructions, replace frequently-used instruction sequences with fewer instructions, and use shorter instructions to handle common tasks of functions. These features all bring effective boosts to code density.”
Dr. Chuan-hua Chang further explained, “AndeStar™ V3 offers compiler support for hardware architecture. That is, it provides a development environment of All-C Embedded Programming for developers to write all their code in C and save the trouble of using assembly language. As to interrupt service routines, AndeStar™ V3 adopts priority-based preemptive interrupt scheme. CPU will handle an interrupt request with the highest priority first, thus speeding up the handling of higher priority interrupts and increasing overall efficiency. Moreover, AndeStar™ V3 also improves debugging capabilities, enabling early discovery of problems that are not very obvious. – With all these features, AndeStar™ V3 not only accelerates time-to-market but also greatly reduces development time, revision, and maintenance overhead.”
Please contact email@example.com for more information about AndeStar™ V3, the new-generation smart low-power backward-compatible 16-/32-bit mixable Instruction Set Architecture.