Press Release Archives - Andes Technology

Andes Technology Showcases Leadership in AI and Automotive Applications at RISC-V Summit Europe 2024

Post author:Peng Murphy
Post published:2024-06-21
Post category:Press Release

Industry-leading RISC-V solutions and live demonstrations of CPU IP are all on display at Booth #8. Discover the latest advancements from Andes’ presentations and posters!

Munich, Germany – June 21, 2024 – Andes Technology Corporation, a leading provider of high efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, is pleased to announce its participation in RISC-V Summit Europe 2024, the prestigious annual event held from June 24 to 28, 2024, in Munich. As a significant contributor, Andes will have presentations to highlight its comprehensive lineup of RISC-V IP and also feature its cutting-edge RISC-V development in the poster session. Andes will demonstrate its leadership in AI and automotive technology as well as showcase the latest QiLai SoC and its development board for RISC-V SW development at booth #8.

Frankwell Lin, Andes Chairman and CEO, will spotlight Andes RISC-V IP portfolio, robust partner ecosystem and latest processors, including an automotive-grade ISO26262 certified core and an out-of-order CPU in the demo theatre speech “Andes High Value RISC-V Processors and Their Applications” on June 25 at 1:10 PM. Chun-Nan Ke, Andes Senior Technical Manager, will delve into how matrix extension and customized quantization instructions for RISC-V can improve general convolutional neural network (CNN) applications in his presentation “Enhancing Convolutional Neural Network Computation with Integrated Matrix Extension” on June 25 at 12:15 PM. Lastly, Vince Wu, Andes Sales Manager, will share compelling customer success stories in the demo talk “Andes RISC-V, Everywhere in Our Life!” on June 25 at 4:20 PM.

Andes, playing a crucial role in the RISC-V community, will exhibit four posters at the poster session. The topics covered include Andes’ ecosystem approach to drive RISC-V adoption in automotive, insights into IOPMP, MobileBERT on RISC-V, and integrated matrix extension. Visit and engage with Andes speakers to gain deeper insights into how these technologies are shaping and revolutionizing RISC-V computing.

The display of QiLai SoC and the Voyager development board will be one of the highlights of the event. The QiLai SoC includes high performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. The Voyager is a 9.6” x 9.6” Micro ATX form factor development board including a QiLai SoC and a multitude of peripherals. The AndesCore™ AX45MP superscalar multicore contains a 2MB Level-2 cache and a MMU (Memory Management Unit) for Linux based applications. The AndesCore™ NX27V vector processor supports a full range of RISC-V standard data types and Andes-enhanced data types optimized for AI workloads. Manufactured at TSMC advanced 7nm process technology, the QiLai SoC and its Voyager development board demonstrate live Andes’ commitment to enable RISC-V software development. The QiLai SoC and the Voyager development board will be exhibited at both Andes booth and the Developer Zone. Take this opportunity to witness the premiere of Andes cutting-edge RISC-V technology.

In addition, Andes will proudly showcase development boards with AndesCore-based SoC from customers at booth #8. These boards include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; an AI development kit with a camera module from Canaan. Visit booth #8 to engage in one-on-one discussion with Andes experts and experience live demonstrations of advanced CPU IP technology.

Details of Andes’ sessions during the RISC-V Summit Europe are as follows:

June 25, Tuesday

12:15-12:30 PM: Presentation “Enhancing Convolutional Neural Network Computation with Integrated Matrix Extension” by Chun-Nan Ke, Senior Technical Manager
1:10-1:20 PM: Demo Theatre Talk “Andes High Value RISC-V Processors and Their Applications” by Frankwell Lin, Chairman and CEO
4:20 PM: 2′ Lightning Talk “Andes RISC-V, Everywhere in Our Life!” by Vince Wu, Sales Manager
All day: Poster “Andes’ Ecosystem Approach to Drive RISC-V Adoption in Automotive Designs” by Samuel Chiang, Deputy Marketing Director
All day: Poster “Deep Insight into IOPMP: Priority and Non-Priority Rules” by Paul Ku, Deputy Director

June 27, Thursday

All day: Poster “MobileBERT on RISC-V: Leveraging IREE Compiler and ACE-RVV Extension for Softmax Acceleration” by Yueh-Feng Lee, Manager of Compute Acceleration Division
All day: Poster “Enhancing Convolutional Neural Network Computation with Integrated Matrix Extension” by Chun-Nan Ke, Senior Technical Manager

For more information, please visit the RISC-V Summit Europe website.

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili, and YouTube! !

Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel

Post author:Ruby Tseng
Post published:2024-06-07
Post category:Press Release

RISC-V: Shaping the Future of AI/ML, Application Processors, Automotive, and Security

San Jose, CA — Jun 6, 2024 — Andes Technology (TWSE: 6533), the leading vendor in high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, unveils its agenda of the annual ANDES RISC-V CON on June 11th at the San Jose Airport DoubleTree Hotel. This year’s theme, “ANDES RISC-V CON: Deep Dive into Automotive/AI/Application Processors and Security Trends,” promises an exhilarating journey into the RISC-V advancements. With over 300 registered attendees, this conference is set to be an industry luminary event, bringing together top-tier experts, researchers, and industry leaders for riveting discussions and groundbreaking insights.

The ANDES RISC-V CON boasts an exceptional lineup of presentations and two dynamic panels featuring key players in the RISC-V ecosystem. The AI panel, moderated by Dylan Patel, Chief Analyst at SemiAnalysis, includes Charlie Cheng from Andes Technology, Chris Walker from Untether AI, Jim Keller from Tenstorrent, and Raja Koduri from Mihira AI. This session will dive deep into “How Open-Source is Transforming AI and Hardware”. Another highlight is the Application Processing panel, moderated by Mark Himelstein, and with panelists consisting of Barna Ibrahim from RISE, Charlie Su from Andes Technology, Lars Bergstrom from Google, and Sandro Pinto from OSYX Technologies. This session will dive deep into how RISC-V eco-system aims at helping RISC-V processor to be used as application processor in a rich OS system, including Android and the others.

The event kicks off at 9:30 AM with a welcome address from Andes Technology’s Chairman and CEO, Frankwell Lin about the RISC-V market outlook, followed with a keynote by Dr. Charlie Su, President & CTO of Andes Technology, titled “Unlocking RISC-V’s Potential in Intelligent Application Processing.” From application processors to AI/ML accelerators, Dr. Su will first give an update on market adoption for RISC-V and show a couple examples of large-scale AI/ML SoCs adopting Andes AI/ML solutions. He will also explore the high-end processor usage scenarios. Marc Evans, Director of Business Development & Marketing at Andes, will discuss Andes’ automotive and security solutions.

The exhibition will display a plethora of exciting RISC-V technologies, including the Andes Qilai testchip, a high-performance SoC with a quad-core RISC-V AX45MP cluster and an NX27V vector processor, designed to accelerate the development and porting of large RISC-V applications. Additionally, there will be an automotive-grade CMOS image sensor demo using the ISO 26262 fully-compliant AndesCore™ N25F-SE by MetaSilicon. Other demos featuring Andes RISC-V cores include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; an AI development kit with a camera module from Canaan; the IT9836 TDDI demo board from ITE; the PC802SCB 5G small cell reference design from Picocom; and a Bluetooth development kit from Telink.

Additionally, renowned companies like Green Hills, IAR, Lauterbach, Piece Makers, RAIN AI, Siemens EDA, Synopsys (Imperas), and TetraMem will have speeches and booths. Alchip, Arteris, Menta, Rambus, RISE, RISC-V International, S2C, Sapeon, SHD, Signature IP, and Sondrel will have booths to engage and interact with attendees.

ANDES RISC-V CON is the ultimate platform for RISC-V designers and developers to engage in meaningful dialogues with global experts. The conference will offer a stimulating and delightful experience, complete with a delicious lunch buffet and a relaxing evening reception. Stay until the end for a chance to win fabulous prizes including iPad in the Lucky Draw!

Best of all, this incredible event is free to attend! Don’t miss out on this extraordinary opportunity to be part of the RISC-V revolution. Register now and join the event for a day of innovation, inspiration, and networking!

👉 Register here: https://www.andestech.com/Andes_RISC-V_CON_2024_US/

About Andes Technology

Rain AI Unveils Andes Technology as Its RISC-V Partner

Post author:Lee Claire
Post published:2024-06-03
Post category:Press Release

Rain AI Licenses Andes AX45MPV and Taps Andes Custom Computing BU to Accelerate Its Launch of Groundbreaking Compute-In-Memory (CIM) Generative AI Solutions

San Francisco, CA, June 03, 2024 – Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announces that Rain AI, a pioneer in compute-in-memory (CIM) technology, licensed Andes’ AX45MPV RISC-V vector processor. Rain AI designs novel accelerator solutions, and the two companies are collaborating to accelerate Rain AI’s product roadmap.

As the world economy embraces generative AI to deliver unprecedented benefits to consumers and business alike, energy consumption stands as a significant hurdle regardless of the deployment points, be it the cloud, edge, and especially the smallest sensors. CIM represents the most promising solution to lower the energy footprint by as much as 50X. By performing computations directly in the memory bit-cells, CIM can dramatically reduce the energy required for matrix operations commonly found in machine learning.

However, CIM by itself cannot completely address the vast and growing number of machine learning operators. A RISC-V CPU is ideal for efficient programming and future-proofing of an CIM-based NPU. The RISC-V architecture allows users to add custom instructions to encapsulate the CIM computing blocks, easing software development efforts. Andes automates this instruction customization process with its automated COPILOT compiler.

Mr. Frankwell Lin, Chairman and CEO of Andes, says, “Andes is honored and excited to have Rain AI as its licensee and partner. As the first RISC-V vector processor provider, we see CIM as an inevitable necessity to enable generative AI applications and therefore have focused on CIM customers. To our knowledge, Rain AI has designed one of the most energy efficient matrix multiplication units using digital CIM technology, so we look forward to Rain AI unveiling its breakthrough solutions.”

Mr. William Passo, CEO of Rain AI, echoed this sentiment, stating, “It is rare to see a vendor who shares the same market and technology vision as us, has best-in-class RISC-V solutions for our technology needs, and can commit resources to help us accelerate our roadmap to significantly reduce the energy required for AI. Running the most advanced models in any form factor is the future of AI, and we are now one step closer with Andes.”

Indeed, Rain AI further taps into Andes’ Custom Computing Business Unit (CCBU) to help accelerate the integration of Andes AX45MPV and the ACE/COPILOT instruction customization with on-site and remote consulting services. Andes’ CCBU is a small team of experts tasked to perform complex customizations and integrations for a few promising cutting-edge licensees.

Both companies can share that AX45MPV and Andes’ unique RISC-V instruction customization solution, ACE/COPILOT both play pivotal roles to complement Rain AI’s groundbreaking CIM hardware, compiler, and runtime software to deliver scalable ML solutions for a variety of deployment points. Rain AI will unveil its accelerator solution in early 2025.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! !

About Rain AI
Rain AI’s mission is to enable advanced and abundant AI everywhere by building the world’s most efficient AI hardware. It creates flexible solutions for generative AI inference and training utilizing novel compute-in-memory CIM technology, RISC-V processing cores, advanced packaging techniques, and optimized ML algorithms. By co-designing hardware with leading AI models, Rain AI sets new standards in AI efficiency and performance. Rain AI investors include Sam Altman, Dan Gross, and Y Combinator. For further information, visit http://www.rain.ai.

Andes Technology Announced the QiLai SoC and the Voyager Development Board

Post author:Ruby Tseng
Post published:2024-05-30
Post category:Press Release

May 30, 2024 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced the QiLai SoC and the Voyager development board to further accelerate the development and porting of large RISC-V applications.

The QiLai SoC chip includes high performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. The AndesCore™ AX45MP superscalar multicore contains a 2MB Level-2 cache, a coherence manger to manage Level-1 cache coherence, and a MMU (Memory Management Unit) for Linux based applications. The AndesCore™ NX27V vector processor with 512KB data cache supports a full range of RISC-V standard data types and Andes-enhanced data types optimized for AI workloads. The NX27V contains an efficient scalar unit and an out-of-order Vector Processing Unit (VPU) with 512-bit vector length (VLEN) and 512-bit data path width (DLEN), capable of generating up to 4 512-bit results per cycle. The NX27V can cooperate with the AX45MP cluster and make QiLai a heterogeneous software development platform where a Linux SMP system and an RTOS or bare-metal system can run simultaneously. The AX45MP and NX27V can run up to 2.2 GHz and 1.5GHz respectively, and the total power consumption of the QiLai SoC is around 5W when running at its full speed.

The Voyager is a 9.6” x 9.6” Micro ATX form factor development board including a QiLai SoC, 16GB of DDR4 SIMM socket, JTAG debugger, USB to UART bridge, I2S Audio Codec, 16Mb SPI Flash for boot code, SD card socket, and several PCIe Gen4 slots that can bridge to many external devices such as GPU card and SSD. The supporting software includes the OpenSUSE Linux distribution, AndeSight™ toolchains, AndeSoft™ software stacks, and AndesAIRE™ NN SDK to convert AI/ML models to executables running on the NX27V vector processor.

“We are excited to announce the QiLai SoC which integrates our widely-adopted AndesCore™ AX45MP multicore and NX27V vector processor,” said Frankwell Lin, Andes Chairman and CEO. “These two processors have been licensed and silicon-proven by many customers though we are still pleased to see them working on our own silicon in the first cut. Manufactured at TSMC advanced 7nm process technology, the QiLai SoC and the Voyager development board demonstrate our commitment to enable the RISC-V software development in real time. Andes will keep its pure-play IP provider position, not going into chip business, this project is a response to provide better processor IP evaluation and application development purpose, and is an excellent resulting fruit from Andes GDR movement in 2021.”

“Andes has been asked by many partners and software developers for silicon-based platforms, where they can develop software for RISC-V more efficiently,” said Dr. Charlie Su, Andes President and CTO. “The Voyager board with the QiLai SoC is our response to that request and a great step towards enabling fast development and evaluation of a wide range of software for RISC-V, and further helps expand the RISC-V ecosystem.”

About Andes

For more information, please visit www.andestech.com or contact info@andestech.com

Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

Andes Technology and Arteris Partner To Accelerate RISC-V SoC Adoption

Post author:Lee Claire
Post published:2024-05-21
Post category:Press Release

Highlights:
– Andes Technology and Arteris partnership aims to support the growing adoption of RISC-V SoCs by mutual customers.
– Focus is on high-performance/low-power RISC-V-based designs across a wide range of markets, including consumer electronics, communications, industrial applications and AI.
– The collaboration showcases integrated and optimized solutions with leading Andes RISC-V processor IPs and Arteris interconnect IP in silicon.

CAMPBELL, Calif. – May 21, 2024 – Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP that accelerates system-on-chip (SoC) creation and Andes Technology (TWSE: 6533), a founding and premier member of RISC-V International and a leading supplier of high-performance/low-power RISC-V processor IP, today announced their partnership to advance innovation for RISC-V based SoC designs for AI, 5G, networking, mobile, storage, AIoT and space applications.

The Andes QiLai RISC-V platform is a development board with a QiLai SoC featuring the Andes’ RISC-V processor IPs along with Arteris FlexNoC interconnect IP used for on-chip connectivity. The QiLai SoC integrates the Andes 64-bit AX45MP multiprocessor (four cores in a cluster) running at 2.2 GHz and the NX27V vector processor running at 1.5 GHz, using Arteris network-on-chip (NoC) interconnect IP with subsystems for PCIe, DDR, SRAM and General Purpose IO using the AMBA AXI protocol. The supporting software includes the OpenSUSE Linux distribution, AndeSight™ toolchains, AndeSoft™ software stacks and AndesAIRE™ NN SDK to convert AI/ML models to executables.

“Even though AndesCore™ AX45MP and NX27V processors are widely used, we are still pleased to see the QiLai SoC achieve first time right on new projects,” said Dr. Charlie Su, Andes Technology’s president and CTO. “Arteris NoC IP was the obvious choice for flexible, high-performance, top-level connectivity across the QiLai SoC. The QiLai platform enhances the rapid development and assessment of RISC-V software, accelerating the expansion of the RISC-V ecosystem.”

“We are excited to partner with Andes Technology and support the QiLai platform interoperability to further accelerate RISC-V technology mainstream adoption,” said Michal Siwinski, chief marketing officer at Arteris. “Our collaboration supports our mission to be the catalyst for SoC innovation so our mutual customers can focus on efficiently creating tomorrow’s breakthroughs.”

Arteris’ FlexNoC non-coherent NoC IP and Ncore cache-coherent NoC IP enable scalable, low latency and power-efficient on-chip communication to achieve superior performance in complex SoC designs. The technology facilitates the integration of high-performance, low-power CPU IPs, enhancing system functionality and interoperability, especially within the growing RISC-V ecosystem. This configurable and adaptable interconnect solution seamlessly interfaces with various components to mitigate risks and expedite time to market. By connecting well-tested CPU IP blocks, system designers can leverage Arteris NoC IPs to enhance the reliability and quality of next-generation SoCs.

Customers can request a devkit featuring the Andes QiLai RISC-V platform at sales@andestech.com. For more information on the partnership and respective products, please contact info@arteris.com and info@andestech.com.

About Arteris
Arteris is a leading provider of system IP for accelerating system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next. Learn more at arteris.com

About Andes Technology
Nineteen years in business and a founding premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

© 2004-2024 Arteris, Inc. All rights reserved worldwide. Arteris, Arteris IP, the Arteris IP logo, and the other Arteris marks found at https://www.arteris.com/trademarks are trademarks or registered trademarks of Arteris, Inc. or its subsidiaries. All other trademarks are the property of their respective owners.

Andes, HiRain, and HPMicro Join Hands to Build RISC-V AUTOSAR Software Ecosystem

Post author:Lee Claire
Post published:2024-05-14
Post category:Press Release

May 14, 2024 —Andes, HiRain, and HPMicro jointly announced that the three parties will cooperate to combine the AndesCore^TM RISC-V processor series, the HPMicro HPM6200 full line of products, and the HiRain Vehicle OS software platform solutions to jointly build the RISC-V ecosystem in the field of automotive electronics. In this cooperation, HiRain’s AUTOSAR product INTEWORK-EAS will be adapted to HPMicro’s full line of HPM6200 products, supporting MCAL software adaptation and engineering integration for HPMicro’s AUTOSAR solutions. HiRain is currently one of the few major AUTOSAR software suppliers with experiences in supporting multiple RISC-V automotive-grade chips. HiRain has been an active player in enabling the RISC-V AUTOSAR ecosystem. The HPM6200 product line has 12 product models, with built-in AndesCore^TM D45 single-core or dual-core RISC-V processor. This series of products has high performance and real-time features, and its application fields include new energy, energy storage, industrial automation, electric vehicles, etc. Through this cooperation, the HPMicro’s chip products will target different application scenarios of automotive electronics with more complete functions and services, enhancing the compatibility of RISC-V technology in the field of automotive electronics. In the future, HiRain and HPMicro will continue to cooperate and continue to provide AUTOSAR software platform solutions for new products.

INTEWORK-EAS is a software product independently developed by HiRain that complies with the AUTOSAR standards. It has a complete AUTOSAR tool chain and is compatible with a variety of mainstream data formats in the industry, such as DBC, LDF, PDX, ODX, ARXML, etc. It supports seamless integration with third-party MCAL toolchains. The solution covers all aspects of standard embedded software, AUTOSAR tool chain, integration services and training, aiming to provide OEMs and suppliers with a stable, reliable, convenient, and easy-to-use AUTOSAR platform. HiRain attaches great importance to the construction of integrated software and hardware solutions. The INTEWORK-EAS series products have been extensively mass-produced and verified on internationally renowned SoC platforms, and HiRain continues to deepen its cooperation with chip companies to jointly provide more integrated software and hardware solutions to the automotive market. For HiRain, this cooperation with HPMicro adds a new important company to its chip partner list and secures its leadership position in the AUTOSAR ecosystem.

HPMicro HPM6200 has adopted the D45 core, which has an 8-stage dual-issue superscalar design, with a main frequency of 600 MHz and performance exceeding 3390 CoreMark and 1710 DMIPS, while supporting IEEE754-compliant single/double-precision floating-point unit (FPU) and RISC-V P (draft) instructions (DSP/SIMD). The D45 core also has a memory subsystem that can support configurable instruction and data caches and local memories which can further improve software performance for the HPM6200 series SoCs. In terms of the application market, the D45 core is very suitable for embedded applications that have special requirements for fast response time and high arithmetic accuracy.

In addition to the high computing power RISC-V CPU, the HPM6200 product also integrates a series of high-performance peripherals and external storage. Further, the HPM6200 series also provides an enhanced PWM control system and a programmable logic array PLA for complex signal generation. Integrating AES-128/256, SHA-1/256 acceleration engines and hardware key managers, the HPM6200 can support hardware and software signature authentication, secure boot, and encrypted execution to prevent illegal code replacement, tampering or copying, further improving safety. HPMicro has completed the ISO9001 quality management certification and ISO 26262 functional safety management system ASIL D certification. The entire line of HPM6200 products has passed the AEC-Q100 G1 certification, with an operating temperature range of -40° to 125°C. After the HiRain INTEWORK-EAS is adapted to the HPM6200, this packaged solution will be fully promoted in the China and rest of the world automotive markets.

Jimmy Zhang, head of HiRain’s embedded software sector, said: “We are very pleased to cooperate with Andes and HPMicro. The three parties jointly create a software and hardware integration solution based on RISC-V to target the growing automotive market. In this era of rapid iteration of chips, it is important to take full advantages of the AUTOSAR middleware. We have strong capabilities in supporting new hardware platforms and this cooperation will once again prove this. In the future, we hope to work with more partners to provide integrated solutions and promote them to the automotive industry.”

Jintao Zeng, CEO of HPMicro, said: “The D45 processor can provide high performance and low-latency for HPMicro’s MCU series products that require ultra-high-speed real-time computing. The CPU performance is excellent and in some test environments it can surpass other competing products. Andes technical support helped us quickly and successfully complete the tape-out of the HPM6000 series. The two teams have a close and efficient cooperation.” “For HPMicro, this AUTOSAR cooperation with HiRain means that the HPMicro products have been widely recognized by the industry, and can drive adoption for high-performance microcontroller products with Andes RISC-V cores into the field of new energy electric vehicles.”

Dr. Charlie Su, President and CTO of Andes Technology, said: “The D45 core and the HPMicro HPM6200 SoC provide developers with a versatile hardware platform, allowing customers to design software with higher performance and more features. The cooperation with HiRain and HPMicro has set a good example for the industry to take a RISC-V MCU into the wider automotive applications. We look forward to participating in more similar cooperations in the future to jointly promote great products to the automotive electronics industry.”

About HiRain Technology
HiRain was founded in 2003 and focuses on providing electronic products, R&D services and high-level intelligent driving overall solutions to customers in the fields of automobiles, unmanned transportation and other fields. Headquartered in Beijing, it has R&D centers and modern factories in Tianjin, Nantong and Malaysia, forming a complete R&D, production, marketing and service system. In line with the concept of “value innovation and customer service”, the company adheres to the strategies of “professional focus”, “technology leadership” and “platform development”. We are committed to becoming a world-class comprehensive electronic system technology service provider, a full-stack solution provider for intelligent connected vehicles, and a leader in high-level intelligent driving MaaS solutions. HiRain is currently one of the few suppliers that can implement full-stack solutions covering intelligent driving electronic products, R&D services and solutions. In the future, HiRain will keep up with the development trend of the automotive industry, adhere to independent innovation, strive to provide high-quality products and services to domestic and foreign customers, and contribute to the development of the automotive industry. For more information about HiRain, please visit https://www.hirain.com/.

About HPMicro Semiconductor
HPMicro is a semiconductor company dedicated to high-performance embedded solutions. Its products cover microcontrollers, microprocessors, and peripheral chips, as well as supporting development tools and ecosystems. The company was established in June 2020, with its headquarters located in Zhangjiang High-Tech Park, Shanghai, and branches in Tianjin, Shenzhen, Suzhou and Hangzhou. The core team comes from the management team of world-renowned semiconductor companies, with more than 15 years of rich R&D and management experience in more than 20 SoCs. HPMicro focuses on product quality, and all products pass strict reliability testing. The high-performance general-purpose MCU product series currently in mass production include HPM6700/6400, HPM6300, HPM6200, HPM5300 and HPM6800. Their performance leads similar international products and has passed AEC-Q100 certification. The company has completed ISO9001 quality management certification and ISO 26262/IEC61508 functional safety management system dual certification, and fully serves the Chinese industrial, automotive and new energy markets. HPMicro will work with world-renowned wafer fabs, packaging and testing plants and other strategic partners to jointly promote technological innovation in the semiconductor fields such as the Internet, industrial automation, and automotive electronics. For more information about HPMicro, please visit www.hpmicro.com.

About Andes Technology
Andes Technology Co., Ltd. was established in Hsinchu Science Park in 2005 and listed on the Taiwan Stock Exchange in 2017 (TWSE: 6533 SIN: US03420C2089; ISIN: US03420C1099). Andes is the founding chief member of the RISC-V International Association and the first mainstream CPU vendor to launch commercial RISC-V vector processors. To meet the strict requirements of today’s electronic equipment, Andes provides highly configurable 32/64-bit high-performance CPU cores, including DSP, FPU, Vector, Superscalar, and Out-of-Order execution, multi-core and functional safety series, which can be applied to various SoCs and application scenarios. Andes also provides a full-featured integrated development environment and comprehensive software/hardware solutions to help customers innovate their SoC designs in a short time. As of the end of 2023, cumulative shipments of Andes-Embedded™ SoC have exceeded 14 billion units. For more information, please visit https://www.andestech.com. Please follow the latest news of Andes Technology through LinkedIn, Twitter, Bilibili and YouTube now.

TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP

Post author:Peng Murphy
Post published:2024-03-28
Post category:Press Release

To enable SoC design teams and Automotive software developers to build optimized and certifiable software solutions.

Munich, Germany – March 27, 2024 – TASKING proudly announces that its ISO 26262 (functional safety) and ISO/SAE 21434 (cybersecurity) compliant compilers now fully support the Andes FuSa certified RISC-V IP. This advancement expands TASKING’s RISC-V tool suite to include compilation, debugging, performance tuning, timing, and coverage analysis tools, providing a comprehensive solution for automotive systems development.

This milestone signifies a significant stride in empowering SoC design teams and automotive software developers to craft highly optimized and certifiable RISC-V based solutions. The newly introduced RISC-V compiler, compliant with ASIL D standards, seamlessly supports both current and forthcoming FuSa certified Andes RISC-V cores. Noteworthy is the compiler’s adaptability to the RISC-V ISA and its extensions, including Andes-specific extensions, ensuring dynamic optimization tailored to the target device, thereby enhancing efficiency and performance.

Andes Technology has achieved remarkable milestones in the automotive market with the introduction of the world’s first RISC-V ISO-26262 fully compliant core, N25F-SE, in 2022. Subsequently, Andes is about to unveil the ASIL-B certified D25F-SE equipped with the RISC-V SIMD/DSP P-extension support (draft), enabling efficient processing of multiple data in a single instruction. Looking ahead, Andes is set to launch processors meeting the ASIL-D standard, including the compact and secure D23-SE, the high-performance D45-SE, and the forthcoming ADAS-capable core in AX60 Series. These advancements underscore Andes’ ability to provide tailored solutions for diverse automotive applications, highlighting its leading expertise in the automotive RISC-V IP market.

“AndesCore™ RISC-V IP, certified with ISO 26262, presents a solid portfolio of automotive processor solution offering unparalleled level of flexibility and efficiency benefits to silicon development,” said Samuel Chiang, Deputy Marketing Director of Andes, “Our partnership with Tasking enables customers in the automotive industry to expedite their development processes, enhancing the performance and robustness of safety-critical RISC-V applications.”

Commenting on the collaboration, Gerard Vink, TASKING’s RISC-V lead, expressed enthusiasm, stating, “We are thrilled to collaborate with Andes and their ecosystem partners. The seamless interoperability of our tools with Andes RISC-V IP across development platforms ranging from virtual prototype to silicon implementations underscores our commitment to providing comprehensive lifecycle support for SoC development teams. Leveraging TASKING’s advanced FuSa and Cybersecurity processes, our users can fast-track compliance efforts, accelerating the time-to-market of RISC-V based automotive software solutions.”

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety, and/or multicore capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Facebook, X, Bilibili and YouTube!

About TASKING
TASKING is a leading provider of development tools headquartered in Munich, Germany, offering high-performance, high quality, safety & security-oriented embedded software development tools for multi-core architectures.,

TASKING’s development tools are used by automotive manufacturers and suppliers, as well as in adjacent markets around the world to realize high-performance applications in safety-critical areas.

The TASKING Embedded Software Development solutions provide an industry-leading ecosystem for your entire software development process. Each TASKING compiler is designed for a certain architecture and meets the specific requirements of your industry, including automotive, industrial, telecommunications and datacom.

As the recognized leader in high-quality, feature- and safety-compliant embedded software development tools, TASKING enables you to create code with best-in-class size and performance with compilers, debuggers and RTOS support for industry-leading microprocessors and microcontrollers.

Since February 2021, TASKING has been majority-owned by financial investor FSN Capital, which has put the group on a long-term growth path following a successful carve-out. For more information visit www.tasking.com or follow us on https://www.linkedin.com/company/tasking-inc.

Seven Years of Uninterrupted Growth: Andes Technology Achieves Milestone Annual Revenue Exceeding NT$1 Billion

Post author:Hsiaoling Lin
Post published:2024-03-21
Post category:Press Release

Andes Technology Is the No. 1 Provider of RISC-V CPU IP According to the SHD Marketing Report

【 Mar. 21, 2024 – Hsinchu, Taiwan】Since its IPO in 2017, Andes Technology (TWSE:6533) has established itself as a leader in the CPU IP sector, achieving a fivefold increase in sales over the past seven years. Andes has invested capital and R&D manpower to accelerate the launch of high-end products to ensure long-term competitiveness and maintain market leadership. It is expected that a competitive product portfolio will create the next wave of revenue peaks.

(Image Source: SHD 2024 RISC-V Market Analysis)

With close monitoring of market dynamics and technology trends and decisive decision-making, Andes has strategically positioned the company to adeptly navigate challenges and seize emerging opportunities, such as bringing innovations in its proprietary AndeStar™ V3 ISA to the RISC-V based AndeStar™ V5 ISA in 2016. In 2023, even when the whole industry was still under inventory pressure, Andes surpassed a significant total shipment milestone of 14 billion Andes-Embedded™ SoCs. According to the SHD marketing report released on Jan 2024, Andes has secured an impressive 30% market share of RISC-V based chip shipping volume through its worldwide customers and is the number one provider of RISC-V CPU IP.

In 2023, the diverse product portfolio offered by Andes has resonated exceptionally well with the market and enabled its sustained growth. Andes has successfully launched the groundbreaking vector processor-AX45MPV, and the industry-revolutionizing automotive ISO 26262 fully certified core N25F-SE. More recently, Andes ventured into the application processor market with the launch of its cutting-edge out-of-order (OOO) processor AX65. AndesCore™ D23 and N225 are also released for the compact, performant, and secure applications. Besides the CPU IPs, Andes has also established a new product line, AndesAIRE™ or Andes AI Runs Everywhere, which offers a comprehensive hardware and software solution designed for edge and end-point inference.

Andes’s unwavering commitment to customer satisfaction has fostered robust relationships with its customers and fortified its market position. The addressable market segments of Andes products span a wide spectrum, encompassing AI/ML, 5G communications, FPGAs, image processing, IoT, MCU/MPU, sensors, storage, TDDI, and wireless connectivity.

Looking ahead, Andes would continue its dedication to innovations, customer satisfaction, and continual adaptation in the dynamic CPU IP licensing market. Below are a set of key drivers underpinning Andes’ growth:

Expansion of AI and HPC Applications: The ongoing surge in demand for AI and High-Performance Computing (HPC) applications, coupled with the requirements for specialized SoC, serves as one of the primary catalysts for Andes. Offering processors enhanced with ACE™ (Andes Automated Custom Extension) to meet the stringent requirements of AI and HPC workloads has significantly contributed to Andes’ market growth.

Increasing Demands for Automotive-Grade (ISO 262626) SoC: As the automotive industry continues to advance, there is a rising need for Automotive-Grade SoCs compliant with the ISO 262626 standard. Andes has seized this trend and is actively catering to the increasing demands for automotive-grade solutions. By offering processors designed to meet the stringent safety and reliability requirements of the automotive sector, Andes is well-positioned to capitalize on this growing market segment, further enhancing its success and market penetration.

Maturity of the RISC-V Ecosystem: By actively participating in the RISC-V International and community with the highest RVI membership and Summit sponsorship, Andes contributes to the RISC-V ecosystem’s fast expansion. Through this effort, Andes remains at the forefront of RISC-V development, fostering a positive cycle benefiting both the company and the ecosystem.

Rise of Multi-Core Heterogeneous SoC: The growing complexity of modern applications, spanning various domains like AIoT, edge computing, and data centers, has led to the rise in multi-core heterogeneous System-on-Chips (SoCs). Andes’ strategic focus on developing a diverse product portfolio aligns seamlessly with the demands of multi-core heterogeneous SoCs. These processors offer the performance and flexibility needed to address the contemporary applications’ requirements.

“Andes Technology’s journey of consistent growth over the past seven years is a testimony to our unwavering determination of staying ahead of industry trends and commitment to customers,” said Frankwell Lin, the Chairman, and CEO of Andes Technology. “We remain dedicated to shaping the future of the CPU IP licensing market with cutting-edge solutions.”

“As Andes charts our roadmap for the future, with ‘Driving Innovations’ as our motto, on one hand, we are developing high-end products that push the boundaries of performance,” remarked Dr. Charlie Su, the CTO and President. “On the other hand, we continue to deliver strong compact processors for power-efficiency and security. Aligning our expertise with the evolving needs of this dynamic industry, our talented team and effective collaboration with customers will continue to drive us forward, shaping the future of high-performance and high-efficiency computing, complying to strict safety demands in automotive SoC, and addressing the ever-emerging AI requirements.”

About ANDES RISC-V CON

ANDES RISC- V CON is the annual RISC-V technology forum hosted by Andes Technology and sponsored by partners. In 2024, the San Jose session will be held in Doubletree by Hilton Hotel on June 11. The 2024 theme is “Deep Dive into Automotive/AI/Application Processing and Security Trends.” It will introduce the flexible RISC-V processors that changes the face of emerging computing and share how Andes assists the RISC-V ecosystem in implementing diversified applications of innovative technologies. Four popular application areas will be focused on: AI/ML, automotive electronics, application processing and security. Many ecosystem partners are invited to give talks and on-site demonstrations. For free registration, please see the official website of Andes RISC-V CON https://www.andestech.com/Andes_RISC-V_CON_2024_US/

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety, and/or multicore capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Facebook, X, Bilibili and YouTube!

Andes Technology: Cultivating Academic Collaboration for Over a Decade with Sustainable Spirit

Post author:Peng Murphy
Post published:2024-03-12
Post category:Press Release

Hsinchu, Taiwan–Mar. 12, 2024 – Andes Technology (TWSE: 6533), since the first agreement signed with National Chiao Tung University in 2010, has actively keeping engaged in industry-academia collaboration. Collaborating with universities across Europe, Asia, and US over a decade, Andes has signed agreements with over 80 universities worldwide.

Andes provides CPU IP Cores licensing, AndeSight™ development tools, software, and hardware/software development platforms to facilitate industry-academia collaboration. From the early self-developed V3 series to the fifth-generation V5 RISC-V processor series starting 2018, Andes has continuously collaborated with globally renowned institutions for research and product licensing. Over a decade, Andes has actively contributed various hardware/software resources, and established joint laboratories with universities and research institutions. The total number of agreements signed with universities worldwide has exceeded 150.

Recently, as the growing focus on ESG indicators, social responsibility emphasizes that companies must not only prioritize profits and shareholder interests but also uphold responsibilities to employees, society, and the environment. With its long-term commitment to academia, Andes has contributed to campus activities and supported young professionals through industry-academia collaboration projects. These initiatives include providing advanced RISC-V core processing unit IP, System-on-Chip (SoC) technology, comprehensive training materials, professional teaching courses, organizing lectures, seminars, conducting unique certification exams, and hosting the creative Andes Cup competition, among other technical services.

RISC-V, well-known for its open, compact, modular, and extensible instruction set, has garnered significant attention in the market, with widespread adoption in Asia-Pacific markets, including Taiwan, Japan, Korea, China, as well as in Europe and the United States. Among the 150+ school agreements signed, Andes provides the latest RISC-V development tools, such as AndeSight™, RISC-V processor debuggers, project implementation examples, verification, and algorithm performance analysis. In terms of curriculum instruction, National Tsing Hua University (NTHU) was among the first to use Andes’ RISC-V development tools in computer architecture and compiler design courses. NTHU also acquired RISC-V FPGA development platforms Corvette F1 and Corvette T1 for instructional experiments and student projects. Over the past two years, there has been a steady increase in enrollment, with over 400 students using the tools annually at NTHU. More than ten universities have incorporated Andes tools and platforms into their teaching, accumulating over 5,000 students in the last five years.

In the realm of processor IP licensing projects, there have been a total of more than a dozen RISC-V projects licensed. These projects span various applications, including biomedical, security, Artificial Intelligence (AI), Internet of Things (IoT), and Machine Learning (ML), with a particular focus on AI research. The licensed processors range from the entry-level processor N22, the 5-stage pipeline processor N25, to the vector processor NX27V and the high-end multicore processor AX45MP. Some research teams obtained licenses for the AndesCore™ V5 RISC-V core and successfully completed tape-out and chip testing at the Taiwan Semiconductor Research Institute of NARLabs. Furthermore, some research teams, based on academic research outcomes, have established startup companies, with updated commercial agreement re-signed, transforming academic licenses into commercial licenses to turn research results into commercial chip for the market.

The Andes Certified Engineer Test (ACET™ Program) is designed to help students obtain certifications and has been recognized by various educational institutions. Students who pass the exam not only meet graduation requirements but also acquire industry skills such as programming, practical operations, and reading product documentation. By integrating these skills with the school’s programming language courses and embedded platform operations, students gain insights into the industry’s product development process and gain early exposure to engineering work. Recently, the platform used for certification exam has transitioned to the RISC-V platform, with a steady growth in registrations, accumulating 2,000 applicants over thirteen years. To encourage more students to participate in RISC-V development, Andes Technology also organizes competition campaigns with substantial cash prizes. The second annual Andes Cup held in 2023, themed “The Great Advance of Artificial Intelligence,” attracted 43 teams from 17 schools.

Frankwell Lin, Chairman and CEO of Andes Technology, stated, “Andes Technology has integrated ESG into annual goals by supporting schools with resources like AndesCore™ and AndeSight™ for research and tech development. This initiative helps cultivate students with practical skills and provides assistance to universities participating in collaborative projects. Through diverse industry-academia cooperation programs, Andes Technology is committed to achieving the dual goals of talent cultivation and industry cooperation, in order to give back to society.”

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety, and/or multicore capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com.
Follow Andes on LinkedIn, Facebook, Twitter, Bilibili and YouTube!

Andes and MachineWare Collaborate on Early RISC-V Software Development for AndesCore™ AX45MPV

Post author:Lee Claire
Post published:2024-02-28
Post category:Press Release

Aachen, Germany and Hsinchu, Taiwan – February 27, 2024 – MachineWare GmbH and Andes Technology (TWSE:6533), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announce an exciting new chapter in their collaboration, marked by a strategic partnership. This synergistic alliance is geared towards the highly innovative AndesCore™ AX45MPV, a cutting-edge multi-core RISC-V vector processor tailored for AI workload acceleration and the application level. In this joint effort, MachineWare lends its support by seamlessly integrating the AX45MPV into their SIM-V high-performance simulation solution. This integration proves invaluable for software developers, enabling them to efficiently handle intricate AI and Linux stack related workloads. The result is a platform that streamlines development, testing, and software verification well in advance of physical prototypes emerging from the fabrication process. This partnership underscores the mutual commitment of MachineWare and Andes Technology to advancing processor technology.

Introducing SIM-V, an offering from MachineWare that holds immense value for developers in the RISC-V landscape. With SIM-V, developers gain the power to thoroughly test and verify their RISC-V-based systems and software applications long before first prototypes are back from the fab. At its core, SIM-V provides a fast Instruction Set Simulator (ISS) that supports all RISC-V standard extensions. One of SIM-V‘s notable strengths is its user-friendly customizability. Through a straightforward extension SDK, developers can swiftly integrate custom instructions, registers, and other elements into the simulator to get instant feedback on their design choices. What makes SIM-V truly special is its SystemC TLM-2.0 integration. This unique combination empowers users to seamlessly introduce their IP models into full system simulation environments, enhancing the versatility of the platform.

The AndesCore™ AX45MPV is a 64-bit 8-stage dual-issue multicore RISC-V vector processor. It incorporates RISC-V GCBP* (*P is a draft version) extensions, and supports SMP Linux with MMU (Memory Management Unit) and up to 48-bit virtual addresses. In addition, it can be configured to up to eight cores with a cache coherence manager and up to 8MB shared L2 cache memory in a cluster. The Vector Processing Unit (VPU) of the AX45MPV implements RISC-V Vector Extension (RVV) version 1.0. It supports configurations of up to 1024-bit vector width (VLEN) and datapath width (DLEN). The AX45MPV is excellent for computations involving large arrays of data such as computer vision, digital signal processing, image processing, machine/deep learning, and scientific computing.

Figure 1: Invoking SIM-V with the AX45MPV configuration.

“We are delighted to join forces with Andes to support the AX45MPV processor in SIM-V,” said Lukas Jünger, Managing Director at MachineWare. “The incorporation of the AX45MPV model enables our common customers to develop RISC-V Linux and AI software stacks and verify their functionality in minutes. This will eliminate bugs and elevate software quality all the while making the overall development process more efficient.”

“Andes’ collaboration with MachineWare is consistent with our continuous effort to broaden RISC-V ecosystem for easy adoption of high-performance simulation tools,” said Samuel Chiang, deputy marketing director of Andes Technology. “We are excited to come together with MachineWare to drive the expansion of the RISC-V ecosystem. And we believe RISC-V’s instruction set architecture will increase innovation and has the potential to transform the AI market.”

About MachineWare GmbH
Founded in 2022 in Aachen, Germany, MachineWare leverages decades of experience in system level simulation and high-performance simulation tooling. Visit https://www.machineware.de/ for more details.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, automotive and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com . Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

About ANDES RISC-V CON
ANDES RISC- V CON is the annual RISC-V technology forum of Andes Technology. In 2024, the Hsinchu session will be held at Amazing Hall Yufeng on March 28; the Shanghai session will be held at DoubleTree by Hilton Hotel Shanghai – Pudong on April 9; the Shenzhen session will be held at Grand Mercure Shenzhen Oriental Ginza Hotel on April 11. The theme of this year is “ANDES RISC-V CON: Deep Dive into Automotive/ AI/ Application Processors and Security Trends.” It will introduce the flexible RISC-V that revolutionizes emerging applications and share Andes latest breakthroughs and innovations in RISC-V. Four popular applications will be focused on: AI, automotive electronics, security and RISC-V’s new field, application processor. Many RISC-V ecosystem partners, including TSMC, are invited to deliver talks and on-site demonstrations.

For more event details and free registration, please visit the official website of the events:

Hsinchu: https://www.andestech.com/Andes_RISC-V_CON_2024_TW/
Shanghai and Shenzhen: https://www.andestech.com/Andes_RISC-V_CON_2024_CN/

About RISC-V
The RISC-V open architecture ISA is under the governance of RISC-V International. Visit https://riscv.org for more details.

MachineWare Contact
Lukas Jünger, Managing Director
E-mail: lukas@mwa.re

Andes Technology Contact
Jonah McLeod, Press Contact, Andes Technology
Tel: +1-510-449-8634
E-mail: Jonahm@andestech.com

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RISC-V: Shaping the Future of AI/ML, Application Processors, Automotive, and Security

Figure 1: Invoking SIM-V with the AX45MPV configuration.

Andes Technology Corporation. All Rights Reserved.