Read more about the article TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor

TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor

By Wenbo Yin, Vice President of IC Design, TetraMem Inc.

Introduction
The rapid proliferation of artificial intelligence (AI) across a growing number of hardware applications has driven an unprecedented demand for specialized compute acceleration not met by conventional von Neumann architectures. Among the competing alternatives, one showing the greatest promise is analog in-memory computing (IMC). Unleashing the potential of multi-level Resistive RAM (RRAM) is making the promise more real today than in the past. Leading this development, TetraMem, Inc., a Silicon Valley based startup, is addressing the fundamental challenges holding this solution back. The company’s unique IMC that employs multi-level RRAM technology provides more efficient, low-latency AI processing that meets the growing needs of modern applications in AR/VR, mobile, IoT, and beyond.

Background on the Semiconductor Industry
The semiconductor industry has seen significant advancements over the past few decades, particularly in response to the burgeoning needs of AI and machine learning (ML). Innovations in chip design have pushed the boundaries of performance and efficiency. However, several intrinsic persistent challenges remain, such as the von Neumann bottleneck and memory wall, which limits data transfer rates between the CPU and memory, and the escalating power consumption and thermal management issues associated with advanced node technologies.

In-memory computing (IMC) represents a ground-breaking computing paradigm shift in how data processing is accomplished. Traditional computing architectures separate memory and processing units, resulting in significant data transfer overheads, especially for the data centric AI applications. On the other hand, IMC integrates memory and processing within the same physical location, enabling faster and more efficient data computations with a crossbar array architecture to further eliminate the large quantity of intermediate data from those matrix operations. This approach is particularly beneficial for AI and ML applications, where large-scale data processing and real-time analytics are critical.

Selecting a suitable memory device for IMC is crucial. Traditional memory technologies like SRAM and DRAM are not optimized for in-memory operations due to their device and cell constraints and their volatility idiosyncrasies. RRAM, with its high density, multilevel capability and non-volatility with superior retention, overcomes these challenges with no refresh needed. The working principle of RRAM involves adjusting the resistance level of the memory cell through controlled voltage or current, mimicking the behavior of synapses in the human brain. This capability makes RRAM particularly suited for analog in-memory computing.

TetraMem has focused its efforts on multi-level RRAM (memristor) technology, which offers several advantages over traditional single level cell memory technologies. RRAM’s ability to store multiple bits per cell and perform efficient matrix multiplications in situ makes it an ideal candidate for IMC. This technology addresses many of the limitations of conventional digital computing, such as bandwidth constraints and power inefficiency.

The RRAM programmable circuit element remembers its last stable resistance level. This resistance level can be adjusted by applying voltage or current. Changes in magnitude and direction of voltage and current applied to the element alters its conductance, thus changing its resistivity. Akin to how a human neuron functions, this mechanism has diverse applications: memory, analog neuron, and, at TetraMem, in-memory computing. The operation of an RRAM is driven by ions. With control of the conductive filament size, ion concentration and height, different multi-levels for cell resistance can be precisely achieved.

Data processed in the same physical location as it is stored with minimum intermediate data movement and storage results in low power consumption. Massive parallel computing by crossbar array architecture with device-level grain cores yields high throughput. And computing by physical laws in this way (Ohm’s law and Kirchhoff’s current law) produces low latency. TetraMem’s nonvolatile compute in-memory cell reduces power consumption by orders of magnitude over a conventional digital von Neumann architecture.

Notable Achievements
TetraMem has achieved significant milestones in the development of RRAM technology. Notably, the company has demonstrated an unprecedented device with 11 bits per cell, achieving over 2,000 levels in a single element. This level of precision represents a major breakthrough in memory compute technology.

Recent publications in prestigious journals such as Nature1 and Science2 highlight TetraMem’s innovative approaches. Techniques to improve cell noise performance and to enhance multi-level IMC have been key areas of advancement. For example, TetraMem has developed proprietary algorithms to suppress random telegraph noise, resulting in superior memory retention and endurance characteristics for RRAM cells.

Operation of IMC
TetraMem’s IMC technology utilizes a crossbar architecture, where each cross-point in the array corresponds to a programmable RRAM memory cell. This configuration allows for highly parallel operations, which are essential for neural network computations. During a Vector-Matrix Multiplication (VMM) operation, input activations are applied to the crossbar array, and the resulting computations are collected on the bit lines. This method significantly reduces the need to transfer data between memory and processing units, thereby enhancing computational efficiency.

Real-World Applications
TetraMem’s first evaluation SoC through the commercial fab process, the MX100 chip (see figure) exemplifies the practical applications of its IMC technology. The chip has been demonstrated in various on-chip demos, showcasing its capabilities in real-world scenarios. One notable demo, the Pupil Center Net (PCN), illustrates the chip’s application in AR/VR for face tracking and authentication monitoring in autonomous vehicles.

To facilitate the adoption of its technology, TetraMem provides a comprehensive Software Development Kit (SDK). This SDK enables developers to define edge AI models seamlessly. Furthermore, the integration with Andes Technology Inc.’s NX27V RISC-V CPU with Vector extensions streamlines operations, making it easier for customers to deploy TetraMem’s solutions in their products.

The TetraMem IMC design is great for matrix multiplication but not as efficient in other functions such as vector or scalar operations. These operations are used frequently in neural networks.  For these functions, Andes provides the flexibility of a CPU plus a vector engine as well as an existing SoC reference design and a mature compiler and library to accelerate our time to market.

TetraMem collaborated with Andes Technology to integrate its IMC technology with Andes’ RISC-V CPU with Vector Extensions. This partnership enhances the overall system performance, providing a robust platform for a variety of AI tasks. The combined solution leverages the strengths of both companies, offering a flexible and high-performance architecture.

Looking ahead, TetraMem is poised to introduce the MX200 chip based on 22nm, which promises even greater performance and efficiency. This chip is designed for edge inference applications, offering low-power, low-latency AI processing. The MX200 is expected to open new market opportunities, particularly in battery-powered AI devices where energy efficiency is paramount.

Conclusion
TetraMem’s advancements in in-memory computing represent a significant leap forward in the field of AI hardware. By addressing the fundamental challenges of conventional computing, TetraMem is paving the way for more efficient and scalable AI solutions. As the company continues to innovate and collaborate with industry leaders like Andes Technology, the future of AI processing looks promising. TetraMem’s solution not only enhances performance but also lowers the barriers to entry for adopting cutting-edge AI technologies.

  1. “Thousands of conductance levels in memristors monolithically integrated on CMOS”, Nature, Mar 2023 https://rdcu.be/c8GWo
  2. “Programming memristor arrays with arbitrarily high precision for analog computing”, Science, Feb 2024 https://www.science.org/doi/10.1126/science.adi9405
Continue ReadingTetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor
Read more about the article Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC

Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC

NX45 Becomes the Only RISC-V Core to Pass Rivos’ Rigorous Verification Process After Extensive Evaluation of Leading RISC-V Cores

San Jose, CA – Sep. 11, 2024 — Rivos Inc., a RISC-V Premier member company focused on accelerating data analytics and Generative AI workloads and Andes Technology, a leading supplier of 32/64-bit RISC-V processor cores and a RISC-V Founding Premier member , announced that Rivos Inc. has licensed the Andes NX45 RISC-V Processor for key control functions in their products.

Rivos was founded in 2021 by industry veterans from Google, Intel, Apple, and PA-Semi and has assembled a world class team of silicon, software, and platform engineers to build industry-leading power efficient, high performance, secure server solutions based on a high-end internally developed RISC-V CPU. 

To run control and scheduling for several key functions in Rivos’ SoC, the highly configurable and extensible Andes NX45 RISC-V processor was chosen because it allows the best tradeoffs in performance and efficiency, while meeting the highest quality standards.

“We are excited to welcome Rivos Inc. to the RISC-V community and wish them tremendous success,” said Dr. Charlie Su, President & CTO of Andes Technology. “We are proud that Rivos chose the NX45 for their project. Rivos’ selection of Andes is a testament to our flexibility, development rigor, and dedication to quality.”

“The growth of the RISC-V ecosystem and customer traction has been remarkable, and we are thrilled to be part of this movement,” said Belli Kuttanna, Co-Founder and CTO at Rivos Inc. “After evaluating several leading RISC-V cores, the Andes NX45 stood out as the only core that passed our proprietary verification process with zero bugs. Its robust configuration options and ease of integration made it the clear choice as our 64-bit control core.”

Rivos recently raised over $250M in an oversubscribed series A-3 funding round to enable the company to tape out its first silicon product, expand manufacturing operations, and scale platform hardware and software engineering efforts.

Andes Technology has been delivering a full range of processing solutions for over 19 years.  Launched in 2019, the AndesCore™ 45-series includes in-order 8-stage dual-issue RISC-V processors with options to support multicore, Linux, and vector processing to meet the demands of many high-end applications.  Andes’ customers benefit from a full-product offering including AndeSight™ IDE, Andes Custom Extension™ (ACE) and related software, and modeling, debug, and trace tools to accelerate their SoC development.

About Rivos Inc.
Rivos has assembled a world class team of silicon, software and platform designers implementing the long term vision of building industry-leading power efficient, high performance, secure server solutions, based on RISC-V, using workload-defined hardware. Rivos supports the intense requirements of the large language models and data analytics through a full solution of optimized chips; combining RISC-V CPUs, a Data Parallel Accelerator, and a reference multi-chip OCP modular server along with a full firmware-to-application open software stack. Rivos is hiring engineering talent across multiple disciplines.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn、Facebook、X、Bilibili  and YouTube! 

 

Continue ReadingRivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC
Read more about the article Resiltech and Andes Technology Announce Collaboration to Deliver Advanced STL Solutions for Andes Automotive-Grade RISC-V Processor IP

Resiltech and Andes Technology Announce Collaboration to Deliver Advanced STL Solutions for Andes Automotive-Grade RISC-V Processor IP

Pontedera, Italy and Hsinchu, Taiwan – Aug 29th, 2024 – Resiltech, a renowned provider of comprehensive security and safety solutions and services, and Andes Technology, a leading supplier of high-performance, low-power RISC-V processor IP are pleased to announce a strategic collaboration to deliver advanced Software Test Library (STL) solutions for Andes’ automotive-grade RISC-V processor IP.

This partnership combines Andes Technology’s expertise in delivering cutting-edge RISC-V processor IP with Resiltech’s proven track record in developing robust STL solutions. Together, they aim to enhance the safety and reliability of automotive electronic systems.

The collaboration will focus on enabling Resiltech to develop advanced STL that can perform safety diagnostic analysis against Andes automotive-grade processor IP line-up. The combined offerings from both companies ensure rigorous fault detection and mitigation, providing automotive OEMs and Tier-1 suppliers with reliable and safe processor solutions.

Resiltech’s STLs are designed to streamline the safety certification process of the target system providing a pre-certified product specifically tailored for the target silicon without the need of any additional activities, an easy and fast SW integration strategy and additional ad-hoc support for the system safety integration.

Andes is committed to delivering functionally safe automotive RISC-V IP, having achieved company-wide ISO-26262 ASIL-D compliance for systematic development process in 2020. Since then, Andes has released the 25-SE series processors, including the N25F-SE and D25F-SE, which have achieved ASIL-B full compliance and gained over a dozen customer projects.  Some customers have already entered mass production and also achieved SoC level ISO-26262 compliance leveraging Andes’ work products. Furthermore, the company plans to release the D45-SE and D23-SE processors including ISO-26262 certification in the coming months, targeting ASIL-D full compliance.

“We are thrilled to partner with Resiltech to bring enhanced safety features to our automotive-grade RISC-V IP,” said Samuel Chiang, marketing director of Andes Technology. “This collaboration underscores our commitment to providing our customers with the most advanced and reliable solutions for automotive applications.”

Francesco Rossi, Safety Solution Director of Resiltech, added, “Our expertise in STL development complements Andes Technology’s innovative processor IP. Together, we are set to provide the automotive industry with a comprehensive solution that not only meets but exceeds the stringent safety requirements of modern vehicles.”

This collaboration marks a significant milestone in advancing the safety of automotive electronic systems, paving the way for the next generation of smart and safe vehicles.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, automotive and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com . Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

About Resiltech
ResilTech is a company providing state-of-the-art solutions and services in safety and security with its 15+ years of experience gained supporting customers operating in Critical Systems. In addition, the company integrates industrial expertise with research and development skills developed while constantly joining, since its foundation, national and international R&D projects. The company is a worldwide leading provider of Software Test Libraries (STLs) for a variety of processing nodes and it is now positioning itself as the reference provider of STLs for the RISC-V ecosystem. For more information, please visit http://www.resiltech.com.

Continue ReadingResiltech and Andes Technology Announce Collaboration to Deliver Advanced STL Solutions for Andes Automotive-Grade RISC-V Processor IP
Read more about the article Andes Technology Showcases Leadership in AI and Automotive Applications at RISC-V Summit Europe 2024

Andes Technology Showcases Leadership in AI and Automotive Applications at RISC-V Summit Europe 2024

Industry-leading RISC-V solutions and live demonstrations of CPU IP are all on display at Booth #8. Discover the latest advancements from Andes’ presentations and posters!

Munich, Germany – June 21, 2024 – Andes Technology Corporation, a leading provider of high efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, is pleased to announce its participation in RISC-V Summit Europe 2024, the prestigious annual event held from June 24 to 28, 2024, in Munich. As a significant contributor, Andes will have presentations to highlight its comprehensive lineup of RISC-V IP and also feature its cutting-edge RISC-V development in the poster session. Andes will demonstrate its leadership in AI and automotive technology as well as showcase the latest QiLai SoC and its development board for RISC-V SW development at booth #8.

Frankwell Lin, Andes Chairman and CEO, will spotlight Andes RISC-V IP portfolio, robust partner ecosystem and latest processors, including an automotive-grade ISO26262 certified core and an out-of-order CPU in the demo theatre speech “Andes High Value RISC-V Processors and Their Applications” on June 25 at 1:10 PM. Chun-Nan Ke, Andes Senior Technical Manager, will delve into how matrix extension and customized quantization instructions for RISC-V can improve general convolutional neural network (CNN) applications in his presentation “Enhancing Convolutional Neural Network Computation with Integrated Matrix Extension” on June 25 at 12:15 PM. Lastly, Vince Wu, Andes Sales Manager, will share compelling customer success stories in the demo talk “Andes RISC-V, Everywhere in Our Life!” on June 25 at 4:20 PM.

Andes, playing a crucial role in the RISC-V community, will exhibit four posters at the poster session. The topics covered include Andes’ ecosystem approach to drive RISC-V adoption in automotive, insights into IOPMP, MobileBERT on RISC-V, and integrated matrix extension. Visit and engage with Andes speakers to gain deeper insights into how these technologies are shaping and revolutionizing RISC-V computing.

The display of QiLai SoC and the Voyager development board will be one of the highlights of the event. The QiLai SoC includes high performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. The Voyager is a 9.6” x 9.6” Micro ATX form factor development board including a QiLai SoC and a multitude of peripherals. The AndesCore™ AX45MP superscalar multicore contains a 2MB Level-2 cache and a MMU (Memory Management Unit) for Linux based applications. The AndesCore™ NX27V vector processor supports a full range of RISC-V standard data types and Andes-enhanced data types optimized for AI workloads. Manufactured at TSMC advanced 7nm process technology, the QiLai SoC and its Voyager development board demonstrate live Andes’ commitment to enable RISC-V software development. The QiLai SoC and the Voyager development board will be exhibited at both Andes booth and the Developer Zone. Take this opportunity to witness the premiere of Andes cutting-edge RISC-V technology.

In addition, Andes will proudly showcase development boards with AndesCore-based SoC from customers at booth #8. These boards include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; an AI development kit with a camera module from Canaan. Visit booth #8 to engage in one-on-one discussion with Andes experts and experience live demonstrations of advanced CPU IP technology.

Details of Andes’ sessions during the RISC-V Summit Europe are as follows:

June 25, Tuesday

  • 12:15-12:30 PM: Presentation “Enhancing Convolutional Neural Network Computation with Integrated Matrix Extension” by Chun-Nan Ke, Senior Technical Manager
  • 1:10-1:20 PM: Demo Theatre Talk “Andes High Value RISC-V Processors and Their Applications” by Frankwell Lin, Chairman and CEO
  • 4:20 PM: 2′ Lightning Talk “Andes RISC-V, Everywhere in Our Life!” by Vince Wu, Sales Manager
  • All day: Poster “Andes’ Ecosystem Approach to Drive RISC-V Adoption in Automotive Designs” by Samuel Chiang, Deputy Marketing Director
  • All day: Poster “Deep Insight into IOPMP: Priority and Non-Priority Rules” by Paul Ku, Deputy Director

June 27, Thursday

  • All day: Poster “MobileBERT on RISC-V: Leveraging IREE Compiler and ACE-RVV Extension for Softmax Acceleration” by Yueh-Feng Lee, Manager of Compute Acceleration Division
  • All day: Poster “Enhancing Convolutional Neural Network Computation with Integrated Matrix Extension” by Chun-Nan Ke, Senior Technical Manager

For more information, please visit the RISC-V Summit Europe website.

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili, and YouTube! ! 

Continue ReadingAndes Technology Showcases Leadership in AI and Automotive Applications at RISC-V Summit Europe 2024
Read more about the article Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel

Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel

RISC-V: Shaping the Future of AI/ML, Application Processors, Automotive, and Security

San Jose, CA — Jun 6, 2024 — Andes Technology (TWSE: 6533), the leading vendor in high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, unveils its agenda of the annual ANDES RISC-V CON on June 11th at the San Jose Airport DoubleTree Hotel. This year’s theme, “ANDES RISC-V CON: Deep Dive into Automotive/AI/Application Processors and Security Trends,” promises an exhilarating journey into the RISC-V advancements. With over 300 registered attendees, this conference is set to be an industry luminary event, bringing together top-tier experts, researchers, and industry leaders for riveting discussions and groundbreaking insights.

The ANDES RISC-V CON boasts an exceptional lineup of presentations and two dynamic panels featuring key players in the RISC-V ecosystem. The AI panel, moderated by Dylan Patel, Chief Analyst at SemiAnalysis, includes Charlie Cheng from Andes Technology, Chris Walker from Untether AI, Jim Keller from Tenstorrent, and Raja Koduri from Mihira AI. This session will dive deep into “How Open-Source is Transforming AI and Hardware”. Another highlight is the Application Processing panel, moderated by Mark Himelstein, and with panelists consisting of Barna Ibrahim from RISE, Charlie Su from Andes Technology, Lars Bergstrom from Google, and Sandro Pinto from OSYX Technologies. This session will dive deep into how RISC-V eco-system aims at helping RISC-V processor to be used as application processor in a rich OS system, including Android and the others.

The event kicks off at 9:30 AM with a welcome address from Andes Technology’s Chairman and CEO, Frankwell Lin about the RISC-V market outlook, followed with a keynote by Dr. Charlie Su, President & CTO of Andes Technology, titled “Unlocking RISC-V’s Potential in Intelligent Application Processing.” From application processors to AI/ML accelerators, Dr. Su will first give an update on market adoption for RISC-V and show a couple examples of large-scale AI/ML SoCs adopting Andes AI/ML solutions. He will also explore the high-end processor usage scenarios. Marc Evans, Director of Business Development & Marketing at Andes, will discuss Andes’ automotive and security solutions. 

The exhibition will display a plethora of exciting RISC-V technologies, including the Andes Qilai testchip, a high-performance SoC with a quad-core RISC-V AX45MP cluster and an NX27V vector processor, designed to accelerate the development and porting of large RISC-V applications. Additionally, there will be an automotive-grade CMOS image sensor demo using the ISO 26262 fully-compliant AndesCore™ N25F-SE by MetaSilicon. Other demos featuring Andes RISC-V cores include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; an AI development kit with a camera module from Canaan; the IT9836 TDDI demo board from ITE; the PC802SCB 5G small cell reference design from Picocom; and a Bluetooth development kit from Telink.

Additionally, renowned companies like Green Hills, IAR, Lauterbach, Piece Makers, RAIN AI, Siemens EDA, Synopsys (Imperas), and TetraMem will have speeches and booths. Alchip, Arteris, Menta, Rambus, RISE, RISC-V International, S2C, Sapeon, SHD, Signature IP, and Sondrel will have booths to engage and interact with attendees. 

ANDES RISC-V CON is the ultimate platform for RISC-V designers and developers to engage in meaningful dialogues with global experts. The conference will offer a stimulating and delightful experience, complete with a delicious lunch buffet and a relaxing evening reception. Stay until the end for a chance to win fabulous prizes including iPad in the Lucky Draw!

Best of all, this incredible event is free to attend! Don’t miss out on this extraordinary opportunity to be part of the RISC-V revolution. Register now and join the event for a day of innovation, inspiration, and networking!

👉 Register here: https://www.andestech.com/Andes_RISC-V_CON_2024_US/

 

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! ! 

 

Continue ReadingAndes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel
Read more about the article Rain AI Unveils Andes Technology as Its RISC-V Partner

Rain AI Unveils Andes Technology as Its RISC-V Partner

Rain AI Licenses Andes AX45MPV and Taps Andes Custom Computing BU to Accelerate Its Launch of Groundbreaking Compute-In-Memory (CIM) Generative AI Solutions

San Francisco, CA, June 03, 2024 – Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announces that Rain AI, a pioneer in compute-in-memory (CIM) technology, licensed Andes’ AX45MPV RISC-V vector processor. Rain AI designs novel accelerator solutions, and the two companies are collaborating to accelerate Rain AI’s product roadmap.

As the world economy embraces generative AI to deliver unprecedented benefits to consumers and business alike, energy consumption stands as a significant hurdle regardless of the deployment points, be it the cloud, edge, and especially the smallest sensors. CIM represents the most promising solution to lower the energy footprint by as much as 50X. By performing computations directly in the memory bit-cells, CIM can dramatically reduce the energy required for matrix operations commonly found in machine learning.

However, CIM by itself cannot completely address the vast and growing number of machine learning operators. A RISC-V CPU is ideal for efficient programming and future-proofing of an CIM-based NPU.  The RISC-V architecture allows users to add custom instructions to encapsulate the CIM computing blocks, easing software development efforts.  Andes automates this instruction customization process with its automated COPILOT compiler.

Mr. Frankwell Lin, Chairman and CEO of Andes, says, “Andes is honored and excited to have Rain AI as its licensee and partner.  As the first RISC-V vector processor provider, we see CIM as an inevitable necessity to enable generative AI applications and therefore have focused on CIM customers.  To our knowledge, Rain AI has designed one of the most energy efficient matrix multiplication units using digital CIM technology, so we look forward to Rain AI unveiling its breakthrough solutions.”

Mr. William Passo, CEO of Rain AI, echoed this sentiment, stating, “It is rare to see a vendor who shares the same market and technology vision as us, has best-in-class RISC-V solutions for our technology needs, and can commit resources to help us accelerate our roadmap to significantly reduce the energy required for AI.  Running the most advanced models in any form factor is the future of AI, and we are now one step closer with Andes.”

Indeed, Rain AI further taps into Andes’ Custom Computing Business Unit (CCBU) to help accelerate the integration of Andes AX45MPV and the ACE/COPILOT instruction customization with on-site and remote consulting services. Andes’ CCBU is a small team of experts tasked to perform complex customizations and integrations for a few promising cutting-edge licensees. 

Both companies can share that AX45MPV and Andes’ unique RISC-V instruction customization solution, ACE/COPILOT both play pivotal roles to complement Rain AI’s groundbreaking CIM hardware, compiler, and runtime software to deliver scalable ML solutions for a variety of deployment points. Rain AI will unveil its accelerator solution in early 2025.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! ! 

About Rain AI
Rain AI’s mission is to enable advanced and abundant AI everywhere by building the world’s most efficient AI hardware. It creates flexible solutions for generative AI inference and training utilizing novel compute-in-memory CIM technology, RISC-V processing cores, advanced packaging techniques, and optimized ML algorithms. By co-designing hardware with leading AI models, Rain AI sets new standards in AI efficiency and performance. Rain AI investors include Sam Altman, Dan Gross, and Y Combinator. For further information, visit http://www.rain.ai.

Continue ReadingRain AI Unveils Andes Technology as Its RISC-V Partner
Read more about the article Andes Technology Announced the QiLai SoC and the Voyager Development Board

Andes Technology Announced the QiLai SoC and the Voyager Development Board

May 30, 2024 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced the QiLai SoC and the Voyager development board to further accelerate the development and porting of large RISC-V applications.

The QiLai SoC chip includes high performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. The AndesCore™ AX45MP superscalar multicore contains a 2MB Level-2 cache, a coherence manger to manage Level-1 cache coherence, and a MMU (Memory Management Unit) for Linux based applications. The AndesCore™ NX27V vector processor with 512KB data cache supports a full range of RISC-V standard data types and Andes-enhanced data types optimized for AI workloads. The NX27V contains an efficient scalar unit and an out-of-order Vector Processing Unit (VPU) with 512-bit vector length (VLEN) and 512-bit data path width (DLEN), capable of generating up to 4 512-bit results per cycle. The NX27V can cooperate with the AX45MP cluster and make QiLai a heterogeneous software development platform where a Linux SMP system and an RTOS or bare-metal system can run simultaneously. The AX45MP and NX27V can run up to 2.2 GHz and 1.5GHz  respectively, and the total power consumption of the QiLai SoC is around 5W when running at its full speed.

The Voyager is a 9.6” x 9.6” Micro ATX form factor development board including a QiLai SoC, 16GB of DDR4 SIMM socket, JTAG debugger, USB to UART bridge, I2S Audio Codec, 16Mb SPI Flash for boot code, SD card socket, and several PCIe Gen4 slots that can bridge to many external devices such as GPU card and SSD. The supporting software includes the OpenSUSE Linux distribution, AndeSight™ toolchains, AndeSoft™ software stacks, and AndesAIRE™ NN SDK to convert AI/ML models to executables running on the NX27V vector processor.

“We are excited to announce the QiLai SoC which integrates our widely-adopted AndesCore™ AX45MP multicore and NX27V vector processor,” said Frankwell Lin, Andes Chairman and CEO. “These two processors have been licensed and silicon-proven by many customers though we are still pleased to see them working on our own silicon in the first cut. Manufactured at TSMC advanced 7nm process technology, the QiLai SoC and the Voyager development board demonstrate our commitment to enable the RISC-V software development in real time. Andes will keep its pure-play IP provider position, not going into chip business, this project is a response to provide better processor IP evaluation and application development purpose, and is an excellent resulting fruit from Andes GDR movement in 2021.”

“Andes has been asked by many partners and software developers for silicon-based platforms, where they can develop software for RISC-V more efficiently,” said Dr. Charlie Su, Andes President and CTO. “The Voyager board with the QiLai SoC is our response to that request and a great step towards enabling fast development and evaluation of a wide range of software for RISC-V, and further helps expand the RISC-V ecosystem.”

 

About Andes

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion.

For more information, please visit www.andestech.com or contact info@andestech.com

Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

Continue ReadingAndes Technology Announced the QiLai SoC and the Voyager Development Board
Read more about the article Andes Technology and Arteris Partner To Accelerate RISC-V SoC Adoption

Andes Technology and Arteris Partner To Accelerate RISC-V SoC Adoption

Highlights:
– Andes Technology and Arteris partnership aims to support the growing adoption of RISC-V SoCs by mutual customers.
– Focus is on high-performance/low-power RISC-V-based designs across a wide range of markets, including consumer electronics, communications, industrial applications and AI.
– The collaboration showcases integrated and optimized solutions with leading Andes RISC-V processor IPs and Arteris interconnect IP in silicon.

CAMPBELL, Calif. – May 21, 2024 – Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP that accelerates system-on-chip (SoC) creation and Andes Technology (TWSE: 6533), a founding and premier member of RISC-V International and a leading supplier of high-performance/low-power RISC-V processor IP, today announced their partnership to advance innovation for RISC-V based SoC designs for AI, 5G, networking, mobile, storage, AIoT and space applications.

The Andes QiLai RISC-V platform is a development board with a QiLai SoC featuring the Andes’ RISC-V processor IPs along with Arteris FlexNoC interconnect IP used for on-chip connectivity. The QiLai SoC integrates the Andes 64-bit AX45MP multiprocessor (four cores in a cluster) running at 2.2 GHz and the NX27V vector processor running at 1.5 GHz, using Arteris network-on-chip (NoC) interconnect IP with subsystems for PCIe, DDR, SRAM and General Purpose IO using the AMBA AXI protocol. The supporting software includes the OpenSUSE Linux distribution, AndeSight™ toolchains, AndeSoft™ software stacks and AndesAIRE™ NN SDK to convert AI/ML models to executables.

“Even though AndesCore™ AX45MP and NX27V processors are widely used, we are still pleased to see the QiLai SoC achieve first time right on new projects,” said Dr. Charlie Su, Andes Technology’s president and CTO. “Arteris NoC IP was the obvious choice for flexible, high-performance, top-level connectivity across the QiLai SoC. The QiLai platform enhances the rapid development and assessment of RISC-V software, accelerating the expansion of the RISC-V ecosystem.”

“We are excited to partner with Andes Technology and support the QiLai platform interoperability to further accelerate RISC-V technology mainstream adoption,” said Michal Siwinski, chief marketing officer at Arteris. “Our collaboration supports our mission to be the catalyst for SoC innovation so our mutual customers can focus on efficiently creating tomorrow’s breakthroughs.”

Arteris’ FlexNoC non-coherent NoC IP and Ncore cache-coherent NoC IP enable scalable, low latency and power-efficient on-chip communication to achieve superior performance in complex SoC designs. The technology facilitates the integration of high-performance, low-power CPU IPs, enhancing system functionality and interoperability, especially within the growing RISC-V ecosystem. This configurable and adaptable interconnect solution seamlessly interfaces with various components to mitigate risks and expedite time to market. By connecting well-tested CPU IP blocks, system designers can leverage Arteris NoC IPs to enhance the reliability and quality of next-generation SoCs.

Customers can request a devkit featuring the Andes QiLai RISC-V platform at sales@andestech.com. For more information on the partnership and respective products, please contact info@arteris.com and info@andestech.com.


About Arteris
Arteris is a leading provider of system IP for accelerating system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next. Learn more at arteris.com

About Andes Technology
Nineteen years in business and a founding premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

© 2004-2024 Arteris, Inc. All rights reserved worldwide. Arteris, Arteris IP, the Arteris IP logo, and the other Arteris marks found at https://www.arteris.com/trademarks are trademarks or registered trademarks of Arteris, Inc. or its subsidiaries. All other trademarks are the property of their respective owners.

Continue ReadingAndes Technology and Arteris Partner To Accelerate RISC-V SoC Adoption
Read more about the article Andes, HiRain, and HPMicro Join Hands to Build RISC-V AUTOSAR Software Ecosystem

Andes, HiRain, and HPMicro Join Hands to Build RISC-V AUTOSAR Software Ecosystem

May 14, 2024 —Andes, HiRain, and HPMicro jointly announced that the three parties will cooperate to combine the AndesCoreTM RISC-V processor series, the HPMicro HPM6200 full line of products, and the HiRain Vehicle OS software platform solutions to jointly build the RISC-V ecosystem in the field of automotive electronics. In this cooperation, HiRain’s AUTOSAR product INTEWORK-EAS will be adapted to HPMicro’s full line of HPM6200 products, supporting MCAL software adaptation and engineering integration for  HPMicro’s AUTOSAR solutions. HiRain is currently one of the few major AUTOSAR software suppliers with experiences in supporting multiple RISC-V automotive-grade chips. HiRain has been an active player in enabling the RISC-V AUTOSAR ecosystem.  The HPM6200 product line has 12 product models, with built-in AndesCoreTM D45 single-core or dual-core RISC-V processor. This series of products has high performance and real-time features, and its application fields include new energy, energy storage, industrial automation, electric vehicles, etc. Through this cooperation, the HPMicro’s chip products will target different application scenarios of automotive electronics with more complete functions and services, enhancing the compatibility of RISC-V technology in the field of automotive electronics. In the future, HiRain and HPMicro will continue to cooperate and continue to provide AUTOSAR software platform solutions for new products.

INTEWORK-EAS is a software product independently developed by HiRain that complies with the AUTOSAR standards. It has a complete AUTOSAR tool chain and is compatible with a variety of mainstream data formats in the industry, such as DBC, LDF, PDX, ODX, ARXML, etc. It supports seamless integration with third-party MCAL toolchains. The solution covers all aspects of standard embedded software, AUTOSAR tool chain, integration services and training, aiming to provide OEMs and suppliers with a stable, reliable, convenient, and easy-to-use AUTOSAR platform. HiRain attaches great importance to the construction of integrated software and hardware solutions. The INTEWORK-EAS series products have been extensively mass-produced and verified on internationally renowned SoC platforms, and HiRain continues to deepen its cooperation with chip companies to jointly provide more integrated software and hardware solutions to the automotive market. For HiRain, this cooperation with HPMicro adds a new important company to its chip partner list and secures its leadership position in the AUTOSAR ecosystem. 

HPMicro HPM6200 has adopted the D45 core, which has an 8-stage dual-issue superscalar design, with a main frequency of 600 MHz and performance exceeding 3390 CoreMark and 1710 DMIPS, while supporting IEEE754-compliant single/double-precision floating-point unit (FPU) and RISC-V P (draft) instructions (DSP/SIMD). The D45 core also has a memory subsystem that can support configurable instruction and data caches and local memories which can further improve software performance for the HPM6200 series SoCs. In terms of the application market, the D45 core is very suitable for embedded applications that have special requirements for fast response time and high arithmetic accuracy.

In addition to the high computing power RISC-V CPU, the HPM6200 product also integrates a series of high-performance peripherals and external storage. Further, the HPM6200 series also provides an enhanced PWM control system and a programmable logic array PLA for complex signal generation. Integrating AES-128/256, SHA-1/256 acceleration engines and hardware key managers, the HPM6200 can support hardware and software signature authentication, secure boot, and encrypted execution to prevent illegal code replacement, tampering or copying, further improving safety. HPMicro has completed the ISO9001 quality management certification and ISO 26262 functional safety management system ASIL D certification. The entire line of HPM6200 products has passed the AEC-Q100 G1 certification, with an operating temperature range of -40° to 125°C. After the HiRain INTEWORK-EAS is adapted to the HPM6200, this packaged solution will be fully promoted in the China and rest of the world automotive markets.

Jimmy Zhang, head of HiRain’s embedded software sector, said: “We are very pleased to cooperate with Andes and HPMicro. The three parties jointly create a software and hardware integration solution based on RISC-V to target the growing automotive market. In this era of rapid iteration of chips, it is important to take full advantages of the AUTOSAR middleware.  We have strong capabilities in supporting new hardware platforms and this cooperation will once again prove this. In the future, we hope to work with more partners to provide integrated solutions and promote them to the automotive industry.”

Jintao Zeng, CEO of HPMicro, said: “The D45 processor can provide high performance and low-latency for HPMicro’s MCU series products that require ultra-high-speed real-time computing. The CPU performance is excellent and in some test environments it can surpass other competing products.  Andes technical support helped us quickly and successfully complete the tape-out of the HPM6000 series. The two teams have a close and efficient cooperation.” “For HPMicro, this AUTOSAR cooperation with HiRain means that the HPMicro products have been widely recognized by the industry, and can drive adoption for high-performance microcontroller products with Andes RISC-V cores into the field of new energy electric vehicles.”

Dr. Charlie Su, President and CTO of Andes Technology, said: “The D45 core and the HPMicro HPM6200 SoC provide developers with a versatile hardware platform, allowing customers to design software with higher performance and more features.  The cooperation with HiRain and HPMicro has set a good example for the industry to take a RISC-V MCU into the wider automotive applications. We look forward to participating in more similar cooperations in the future to jointly promote great products to the automotive electronics industry.”

 

About HiRain Technology
HiRain was founded in 2003 and focuses on providing electronic products, R&D services and high-level intelligent driving overall solutions to customers in the fields of automobiles, unmanned transportation and other fields. Headquartered in Beijing, it has R&D centers and modern factories in Tianjin, Nantong and Malaysia, forming a complete R&D, production, marketing and service system. In line with the concept of “value innovation and customer service”, the company adheres to the strategies of “professional focus”, “technology leadership” and “platform development”. We are committed to becoming a world-class comprehensive electronic system technology service provider, a full-stack solution provider for intelligent connected vehicles, and a leader in high-level intelligent driving MaaS solutions. HiRain is currently one of the few suppliers that can implement full-stack solutions covering intelligent driving electronic products, R&D services and solutions. In the future, HiRain will keep up with the development trend of the automotive industry, adhere to independent innovation, strive to provide high-quality products and services to domestic and foreign customers, and contribute to the development of the automotive industry. For more information about HiRain, please visit https://www.hirain.com/.

 

About HPMicro Semiconductor
HPMicro is a semiconductor company dedicated to high-performance embedded solutions. Its products cover microcontrollers, microprocessors, and peripheral chips, as well as supporting development tools and ecosystems. The company was established in June 2020, with its headquarters located in Zhangjiang High-Tech Park, Shanghai, and branches in Tianjin, Shenzhen, Suzhou and Hangzhou. The core team comes from the management team of world-renowned semiconductor companies, with more than 15 years of rich R&D and management experience in more than 20 SoCs. HPMicro focuses on product quality, and all products pass strict reliability testing. The high-performance general-purpose MCU product series currently in mass production include HPM6700/6400, HPM6300, HPM6200, HPM5300 and HPM6800. Their performance leads similar international products and has passed AEC-Q100 certification. The company has completed ISO9001 quality management certification and ISO 26262/IEC61508 functional safety management system dual certification, and fully serves the Chinese industrial, automotive and new energy markets. HPMicro will work with world-renowned wafer fabs, packaging and testing plants and other strategic partners to jointly promote technological innovation in the semiconductor fields such as the Internet, industrial automation, and automotive electronics. For more information about HPMicro, please visit www.hpmicro.com.

About Andes Technology
Andes Technology Co., Ltd. was established in Hsinchu Science Park in 2005 and listed on the Taiwan Stock Exchange in 2017 (TWSE: 6533 SIN: US03420C2089; ISIN: US03420C1099). Andes is the founding chief member of the RISC-V International Association and the first mainstream CPU vendor to launch commercial RISC-V vector processors. To meet the strict requirements of today’s electronic equipment, Andes provides highly configurable 32/64-bit high-performance CPU cores, including DSP, FPU, Vector, Superscalar, and Out-of-Order execution, multi-core and functional safety series, which can be applied to various SoCs and application scenarios. Andes also provides a full-featured integrated development environment and comprehensive software/hardware solutions to help customers innovate their SoC designs in a short time. As of the end of 2023, cumulative shipments of Andes-Embedded™ SoC have exceeded 14 billion units. For more information, please visit https://www.andestech.com. Please follow the latest news of Andes Technology through LinkedIn, Twitter, Bilibili and YouTube now.

 

Continue ReadingAndes, HiRain, and HPMicro Join Hands to Build RISC-V AUTOSAR Software Ecosystem
Read more about the article TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP

TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP

To enable SoC design teams and Automotive software developers to build optimized and certifiable software solutions.

Munich, Germany – March 27, 2024 – TASKING proudly announces that its ISO 26262 (functional safety) and ISO/SAE 21434 (cybersecurity) compliant compilers now fully support the Andes FuSa certified RISC-V IP. This advancement expands TASKING’s RISC-V tool suite to include compilation, debugging, performance tuning, timing, and coverage analysis tools, providing a comprehensive solution for automotive systems development.


This milestone signifies a significant stride in empowering SoC design teams and automotive software developers to craft highly optimized and certifiable RISC-V based solutions. The newly introduced RISC-V compiler, compliant with ASIL D standards, seamlessly supports both current and forthcoming FuSa certified Andes RISC-V cores. Noteworthy is the compiler’s adaptability to the RISC-V ISA and its extensions, including Andes-specific extensions, ensuring dynamic optimization tailored to the target device, thereby enhancing efficiency and performance.


Andes Technology has achieved remarkable milestones in the automotive market with the introduction of the world’s first RISC-V ISO-26262 fully compliant core, N25F-SE, in 2022. Subsequently, Andes is about to unveil the ASIL-B certified D25F-SE equipped with the RISC-V SIMD/DSP P-extension support (draft), enabling efficient processing of multiple data in a single instruction. Looking ahead, Andes is set to launch processors meeting the ASIL-D standard, including the compact and secure D23-SE, the high-performance D45-SE, and the forthcoming ADAS-capable core in AX60 Series. These advancements underscore Andes’ ability to provide tailored solutions for diverse automotive applications, highlighting its leading expertise in the automotive RISC-V IP market.

 

“AndesCore™ RISC-V IP, certified with ISO 26262, presents a solid portfolio of automotive processor solution offering unparalleled level of flexibility and efficiency benefits to silicon development,” said Samuel Chiang, Deputy Marketing Director of Andes, “Our partnership with Tasking enables customers in the automotive industry to expedite their development processes, enhancing the performance and robustness of safety-critical RISC-V applications.”


Commenting on the collaboration, Gerard Vink, TASKING’s RISC-V lead, expressed enthusiasm, stating, “We are thrilled to collaborate with Andes and their ecosystem partners. The seamless interoperability of our tools with Andes RISC-V IP across development platforms ranging from virtual prototype to silicon implementations underscores our commitment to providing comprehensive lifecycle support for SoC development teams. Leveraging TASKING’s advanced FuSa and Cybersecurity processes, our users can fast-track compliance efforts, accelerating the time-to-market of RISC-V based automotive software solutions.”

 

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety, and/or multicore capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Facebook, X, Bilibili and YouTube! 


About TASKING
TASKING is a leading provider of development tools headquartered in Munich, Germany, offering high-performance, high quality, safety & security-oriented embedded software development tools for multi-core architectures.,


TASKING’s development tools are used by automotive manufacturers and suppliers, as well as in adjacent markets around the world to realize high-performance applications in safety-critical areas.


The TASKING Embedded Software Development solutions provide an industry-leading ecosystem for your entire software development process. Each TASKING compiler is designed for a certain architecture and meets the specific requirements of your industry, including automotive, industrial, telecommunications and datacom.


As the recognized leader in high-quality, feature- and safety-compliant embedded software development tools, TASKING enables you to create code with best-in-class size and performance with compilers, debuggers and RTOS support for industry-leading microprocessors and microcontrollers.


Since February 2021, TASKING has been majority-owned by financial investor FSN Capital, which has put the group on a long-term growth path following a successful carve-out. For more information visit www.tasking.com or follow us on https://www.linkedin.com/company/tasking-inc.

Continue ReadingTASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP