TASKING, Andes, and MachineWare Team Up to Facilitate Rapid Development of RISC-V ASIL Compliant Automotive Silicon

To support SoC design teams in the realm of firmware and MCAL development

Munich, Germany – Nov. 6, 2023 – TASKING’s system-level verification and debugging tools now support the Andes RISC-V ISO 26262 certified Processor IPs and associated MachineWare Virtual Models. This collaboration equips SoC design teams with automotive-grade RISC-V IPs and the appropriate tools for early firmware and MCAL (Microcontroller Abstraction Layer) development.

TASKING has been serving the global automotive industry for more than 30 years with software development tools certified for functional safety and cybersecurity. The toolset released as part of the collaboration provides the capabilities for multi-core, multi-hart, verification, debugging, performance tuning, timing, and coverage analysis. The toolset can be used with Andes RISC-V development boards and MachineWare high-performance virtual prototyping solutions. Moreover, the innovative TASKING iSYSTEM debug adapters will be available to support Andes RISC-V processors to enable the connection with the toolset.

Andes Technology, a prominent provider of high-efficiency, low-power 32/64-bit RISC-V processor cores, introduced the first ISO 26262 fully compliant RISC-V processor IP – N25F-SE in 2022 with ASIL-B certification. Andes is also gearing up to unveil the ASIL-B certified D25F-SE equipped with RISC-V P-extension (SIMD/DSP) ISA draft for efficient manipulation of multiple data in a single instruction in the fourth quarter of 2023. Furthermore, Andes is working to deliver mission-critical ASIL-D certified cores based on their popular CPU IPs. The goal of this partnership is to offer comprehensive support for functional safety solution development, particularly in the realm of firmware and MCAL development. These resources will subsequently be employed by their customers within the automotive supply chain.

MachineWare’s ultra-fast virtual prototypes facilitate simulation of complex hardware/software systems for software analysis, verification and development as well as architecture exploration. With SIM-V MachineWare offers a high-speed RISC-V simulator that can be integrated in a full-system simulation, or Virtual Platform (VP) to simulate entire SoCs or ECUs. Besides pre-silicon availability, VPs offer many advantages over physical prototypes, as they enable for deep, non-intrusive introspection and are extremely scalable either on-premise or in the cloud.

The combination of products from the three companies enables users to switch seamlessly between virtual and physical SoCs, applying the same tools and automation scripts without any changes to the users’ process. This allows software developers to start the development process before silicon is available and identify and fix potential bugs and security issues at an early stage, shortening time-to-market.

Gerard Vink, responsible for RISC-V at TASKING, is excited about the collaboration of the three companies: “This partnership offers an integrated solution needed to drive the adoption of RISC-V based SoCs in the automotive domain. The certified IPs and tools reduce the efforts of all parties in the supply chain to comply with functional safety and cybersecurity requirements, enabling them to focus on innovation and product differentiation.”

“Andes’ ISO 26262 certified RISC-V IP offers solid, unprecedented flexibility and efficiency in silicon development,” said Samuel Chiang, Deputy Marketing Director of Andes, “Together with TASKING and MachineWare, we empower customers in the automotive industry to accelerate their development efforts, ensuring the successful achievement of functional safety and cybersecurity protection.”

“Our ultra-fast SIM-V functional RISC-V simulator empowers engineers to simulate complex hardware/software systems long before physical prototypes are even available. This speeds up the development process and reduces expensive bugs,” said Lukas Jünger, co-founder of MachineWare. “We are proud to collaborate with TASKING and Andes to offer our customers the tools they need for developing SoCs for the automotive industry.”

For more detailed information about the partnership and the three companies, please visit www.tasking.com, www.andestech.com and www.machineware.de.

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly listed company  (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! 

About MachineWare
Established in 2022 in Aachen, Germany, MachineWare is a pioneering company specializing in the creation of high-performance simulators for entire electronic systems, commonly referred to as Virtual Platforms (VPs). These cutting-edge VPs are designed to execute unmodified target software, serving as indispensable tools for development, verification, and architecture exploration.

One of MachineWare’s flagship offerings, SIM-V, stands out as a versatile and rapid solution tailored for virtualizing RISC-V systems. SIM-V empowers users to accelerate their RISC-V software development process, allowing them to meet and exceed their schedules by helping to identify software defects, such as bugs and vulnerabilities long before physical prototypes are available.

MachineWare’s products and services simplify hardware/software integration by providing a unified toolset for both hardware and software designers early in the system design cycle. This approach facilitates a smoother development process and superior end products. Visit https://www.machineware.de for more details.

About TASKING
TASKING is a leading provider of development tools headquartered in Munich, Germany, offering high-performance, high quality, safety & security-oriented embedded software development tools for multi-core architectures.

TASKING’s development tools are used by automotive manufacturers and suppliers, as well as in adjacent markets around the world to realize high-performance applications in safety-critical areas.

The TASKING Embedded Software Development solutions provide an industry-leading ecosystem for your entire software development process. Each TASKING compiler is designed for a certain architecture and meets the specific requirements of your industry, including automotive, industrial, telecommunications and datacom.

As the recognized leader in high-quality, feature- and safety-compliant embedded software development tools, TASKING enables you to create code with best-in-class size and performance with compilers, debuggers and RTOS support for industry-leading microprocessors and microcontrollers.

Since February 2021, TASKING has been majority-owned by financial investor FSN Capital, which has put the group on a long-term growth path following a successful carve-out. For more information visit www.tasking.com or follow us on https://www.linkedin.com/company/tasking-inc.

Continue ReadingTASKING, Andes, and MachineWare Team Up to Facilitate Rapid Development of RISC-V ASIL Compliant Automotive Silicon

Ansys medini Accelerates Andes’ Development of Automotive-Grade IP

Hsinchu, Taiwan – Nov. 2, 2023 – The automotive industry imposes stringent requirements on Functional Safety. For semiconductor companies involved in automotive chips and even further upstream in Silicon Intellectual Property (SIP), obtaining ISO 26262 certification is a fundamental requirement for product penetration into automotive applications. Andes Technology is actively developing a portfolio of automotive-grade IP products to enhance the efficiency of product functional safety verification activities. To streamline ISO 26262 verification and to integrate verification information conveniently, the decision was made to introduce Ansys medini to achieve the automation and modulization of safety analysis process.

In the field of RISC-V CPU IP for the automotive market, Andes Technology has achieved remarkable milestones. In 2020, Andes became the world’s first RISC-V supplier to have its development process certified to ISO-26262 ASIL-D standard. In 2022, Andes became the world’s first RISC-V supplier to have its IP fully certified to ISO-26262 ASIL-B standard, with the solution adopted in over ten customer projects. Andes is proactively addressing the demands of the automotive market by planning a comprehensive range of automotive IP products, covering RISC-V IP solutions with different functional safety levels from ASIL-B to ASIL-D, along with varying processor performance levels and feature sets. In 2023, Andes is set to officially introduce an 8-stage pipeline dual-issue processor that meets the ASIL-D standard. This signifies their ability to provide tailored solutions for diverse automotive applications, highlighting their leading expertise in the automotive RISC-V IP market. Adopting Ansys medini is an important step in this direction.

Eric Huang, Associate Vice President of Quality and Safety Management at Andes Technology, pointed out that for players in the automotive supply chain, obtaining certifications such as ISO 26262 is a critical factor determining market entry and approving technical strength. For IP suppliers to attain these certifications, two main challenges need to be addressed: the first is to introduce the complicated and rigorous ISO 26262 requirements efficaciously. The second is to develop and actualize the safety features competitively. The more products are developed for automotive market, the more crucial is to boost the safety analysis efficiency to speed up design verification.

Dr. Alex Chen, Director of the VLSI at Andes Technology, pointed out that the design verification process often involves the use of various analysis tools, such as FMEDA and FTA. However, the documents generated by these tools are typically stored in different formats and dispersed. This process is highly cumbersome and necessitates constant checks to ensure data consistency and accuracy. In the event of data changes, manual effort is needed to update the data, making it a mental-intensive activity.

Therefore, having an automated tool that can link the documents generated by different analysis tools and consistently update them to the latest versions is important for developing automotive-grade IP. Ansys medini provides an integrated environment that not only includes the analysis tools required by standards like ISO 26262 but also automates data transfer. This not only eases the loading on document verification but also enhances the accuracy of related data. As a result, Andes IP solutions can obtain ISO 26262 certification more quickly.

“The innovation cycle in the automotive industry is accelerating, but the requirements for functional safety are non-negotiable. Therefore, whether it’s automotive OEMs, Tier 1, Tier 2, or semiconductor companies further upstream, they are all seeking automation tools that can expedite functional safety analysis and verification processes.” Roger Lee, Ansys Taiwan Country Manager, stated. “Currently, there are many standalone tools in the market that meet the specific requirements of individual ISO 26262 verification items. However, Ansys medini is the only tool that can further achieve data integration and interfacing, enabling comprehensive automation of data generation, consolidation, and maintenance, with the added benefit of data reuse. This unique advantage has gained widespread recognition and adoption throughout the automotive industry’s supply chain. There are high expectations that Ansys medini will bring enhanced competitiveness to Andes Technology’s automotive-grade IP business.”

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! 

Continue ReadingAnsys medini Accelerates Andes’ Development of Automotive-Grade IP

Andes Technology to Exhibit Groundbreaking RISC-V Solutions for AI and Automotive at RISC-V Summit North America 2023

Discover the cutting-edge insights from Andes’ presentations and explore live demonstrations of CPU IP technology at Booth #D4 and get your opportunity to seize lucky draw prizes, including mobile phones!

SAN JOSE, CA – Oct. 31, 2023 – Andes Technology Corporation (TWSE: 6533), a leading provider of high efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, announces its significant role as the diamond sponsor in RISC-V Summit North America, the prestigious annual event held from November 6 to 8, 2023 in Santa Clara. As a key contributor, Andes will deliver a keynote speech about AI/ML SoC solutions based on RISC-V and the latest on Andes RISC-V processors to enable them. Andes will also address three presentations and two demo talks focused on AI/ML solutions, automotive-grade IP, IOPMP, RISC-V vector technology and more. During the event, Andes will showcase its state-of-the-art RISC-V CPU IP offerings at booth #D4.

Andes President and CTO, Dr. Charlie Su, will present why RISC-V is a perfect solution to bring intelligence everywhere and introduce Andes product portfolio in the keynote speech “Taking RISC-V Intelligence Everywhere” on November 8 at 9:55 AM. Dr. Paul Ku, Deputy Director of Andes and chair of IOPMP task group, will give an update of IOPMP spec on November 6 at 14:55 PM. Chun-Nan Ke, Senior Technical Manager, will explore the Andes proposal for RISC-V matrix multiplication instructions which enhance significant performance for AI applications in his presentation “Advancing AI Computing with Optimized Matrix Multiplication Techniques with RISC-V CPU” on November 7 at 12:10 PM. Furthermore, Dr. Heng-Kuan Lee, Senior Manager, will discuss how to enhance efficiency and accuracy of computations in transformer models in “Enhancing Transformers: Accelerating Nonlinear Function Computation on RISC-V Vector Processor” on November 7 at 15:15 PM. Lastly, Hubert Chung, FAE Manager, will deliver a demo talk “AI Solution – AndesAIRE, including HW and SW” on November 7 at 12:55 PM . Marvin Chao, Director of Solution Architect, will give the other demo talk “Andes Technology RISC-V Functional Safety Solutions” on November 7 from 11:10 to 11:20 AM at the demo theater.

In addition, Andes will proudly display development boards integrated with Andes-Embedded™ technology at the Developer Zone. These boards include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; high-performance industrial-grade microcontrollers from HPMicro; one of the first complete RISC-V microcontrollers with an embedded FPGA from Gowin; and an Arduino-compatible development board based on a wireless SoC from Andes. Seize the opportunity to understand how customers are working with Andes products for various applications by visiting the Developer Zone. Also, Andes will announce its new safety-enhanced core, D25F-SE, at the Launchpad session.

Besides presentations and live demo, RISC-V Board of Director and Andes CEO, Frankwell Lin, will join the Media Panel Luncheon “RISC-V is HERE: Future Outlook with Invested RISC-V Leaders” on November 7 at 13:00 PM. Join the discussion to discover the remarkable progress in the RISC-V ecosystem across diverse applications and witness how RISC-V is empowering companies with advanced design flexibility.

This event presents a valuable opportunity for RISC-V enthusiasts to reserve one-on-one discussion with Andes experts to explore RISC-V solutions in-depth. Andes invites you to visit booth #D4 at the RISC-V Summit and experience live demonstrations of its leading-edge CPU IP technology. Stop by Andes’ booth for a chance to win fantastic prizes, including mobile phones!

Details of Andes’ sessions during the RISC-V Summit are outlined below:

  • November 6 (Member Day),
    • 14:55-15:20 PM: Presentation “IOPMP Update” by Dr. Paul Ku, Deputy Technical Director
  • November 7 (Day 1),
    • 12:10-12:30 PM: Presentation “Advancing AI Computing with Optimized Matrix Multiplication Techniques with RISC-V CPU” by Chun-Nan Ke, Senior Technical Manager, and Dr. Heng-Kuan Lee, Senior Manager
    • 13:00-13:55 PM: Media Panel Luncheon “RISC-V is HERE: Future Outlook with Invested RISC-V Leaders” by Frankwell Lin, Chairman and CEO
    • 12:55-13:05 PM: Demo “AI Solution – AndesAIRE, including HW and SW” by Hubert Chung, FAE Manager
    • 15:15-15:35 PM: Presentation “Enhancing Transformers: Accelerating Nonlinear Function Computation on RISC-V Vector Processor” by Dr. Heng-Kuan Lee, Senior Manager, and Simon Wang, Senior Technical Manager
  • November 8 (Day 2),
    • 9:55-10:10 AM: Keynote “Taking RISC-V Intelligence Everywhere” by Charlie Su, CTO and President
    • 11:10-11:20 AM: Demo “Andes Technology RISC-V Functional Safety Solutions” by Marvin Chao, Director of Solution Architect

For more information, please visit the RISC-V Summit website.

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Facebook, Weibo, Twitter, Bilibili and YouTube! 

Continue ReadingAndes Technology to Exhibit Groundbreaking RISC-V Solutions for AI and Automotive at RISC-V Summit North America 2023

Andes Technology Unveils Andes D23 and N225 Cores Pioneering the Next Generation of Compact, Performant, and Secure RISC-V Processor Technology

Hsinchu, Taiwan – Oct. 17, 2023 – Andes Technology, the renowned supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, proudly announces the release of its latest innovation – the AndesCore™ D23 and N225 RISC-V processors. Specifically designed to cater to the dynamic needs of the Internet of Things (IoT) and embedded systems, these cores epitomize Andes’ unwavering commitment to delivering cutting-edge technology for the interconnected world.

The D23 and N225 cores have been meticulously engineered with compactness, performance-efficiency, low-power consumption, flexibility, and security as top priorities. These cores empower IoT and embedded chip and device manufacturers to meet the burgeoning demands of a rapidly evolving market while minimizing power usage and ensuring robust security.

Andes announced the popular N22, a 2-stage pipeline AndesCore implementing RV32I/EMAC ISA back in February 2019, targeting deeply embedded processing and having a performance of 3.95 Coremark/MHz and 1.8 DMIPS/MHz. The D23 and N225 are revamped designs with a new microarchitecture and the latest RISC-V extensions (details below) to offer better performance, smaller code size, and more security support. They provide a good migration path for customers looking to upgrade their N22 designs or kick-off a new design today.

Common Key Features of AndesCore D23 and N225:
Latest RISC-V Extensions Support: The N225 implements the RV32 IMACBZce non-privileged extensions as well as Machine/User modes and Enhanced Physical Memory Protection (ePMP). The D23 additionally supports the FDKP extensions (Single/Double-Precision Floating-Point, Scalar Crypto and Packed SIMD/DSP draft), and CMO (Cache Management Operations) extension. The D23 is also incorporated with Supervisor mode and its associated PMP (sPMP) for higher security.

Compact Size: Both cores feature a highly compact design with a 3-stage pipeline, primarily supporting single instruction issue with some dual-issue capability. This makes them exceptionally well-suited for space- and memory-constrained IoT and embedded applications, including wearables, sensors, and smart home devices.

High Performance: Both cores achieve industry-leading performance in their class, boasting outstanding benchmark scores such as 4.55 (D23) and 4.4 (N225) Coremark/MHz, and 2.08 (D23) and 1.92 (N225) DMIPS/MHz, respectively. They are capable of operating at high frequencies across various technology nodes such as near 800 MHz at 28nm, providing the necessary computing power for edge IoT devices with ever-increasing performance and feature demands.

Power Management: Both cores support advanced power management technologies such as PowerBrake and Wait-For-Interrupt (WFI) and Wait-For-Event (WFE), ensuring prolonged battery life for many types of untethered IoT devices.

Small Code Size: The N22 already offers industry-leading code size with Andes CoDense™ technology. With the addition of the new RISC-V Zce code size reduction extension, the D23 and N225 further reduce 4.4% code size for the Embench-IoT benchmark, compared to the N22. This provides additional memory cost-saving for Andes customers.

Flexibility: Both cores offer extensive configurability, including optimized multipliers for performance or area, optional static or dynamic branch prediction, various combinations of privilege modes, instruction and data Local Memories with sizes from 1 KB to 512 MB, and 2-wire or 4-wire JTAG debug interface. Designers can tailor these features to address their specific application requirements.

Ease of SoC Integration: To simplify integration into System-on-Chip (SoC) designs, both cores support either Core-Local Interrupt Controller (CLIC) for the single-CPU SoC or Platform-level Interrupt Controller (PLIC) for multiple-CPU SoC, rich options for AMBA interfaces, private machine timers or platform machine timers, and instruction trace interfaces.

In addition to the above-mentioned shared features and latest RISC-V extensions, the D23 core boasts additional capabilities, including built-in instruction and data caches, and ECC soft error protection for all cache and local memories. It can also seamlessly integrate with the powerful ACE™ (Andes Custom Extension) to support custom instructions for Domain-Specific Acceleration (DSA) and has a roadmap to include a functional safety derivative. These expanded capabilities open up opportunities for the D23 to serve a wider range of segments in automotive and industrial control applications.

Dr. Charlie Su, President and CTO of Andes Technology, expressed his enthusiasm for the release of these cores, stating, “The D23 and N225 mark a significant milestone in our commitment to providing innovative solutions for the IoT and embedded segments. With their compact design, power efficiency, and robust security features, these cores are poised to set new industry standards. We believe they will empower designers and developers to create cutting-edge products that can thrive in the fast-paced world of IoT.”

The D23/N225 have been licensed out and several companies are actively evaluating them. Their overall features will be developed and delivered in two phases. For more information about these cores, please visit the Andes Technology website.

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! 

Continue ReadingAndes Technology Unveils Andes D23 and N225 Cores Pioneering the Next Generation of Compact, Performant, and Secure RISC-V Processor Technology

Andes Announces General Availability of the New AndesCore™ RISC-V Multicore Vector Processor AX45MPV

Hsinchu, Taiwan – Sep. 7, 2023 –  Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today proudly announces general availability of the high-performance AndesCore™ AX45MPV multicore vector processor IP. The AX45MPV is the third generation of the award winning AndesCore™ vector processor series. Equipped with powerful RISC-V vector processing and parallel execution capability, it targets the applications with large volumes of data such as ADAS, AI inference and training, AR/VR, multimedia, robotics, and signal processing.

Andes and Meta started collaboration on datacenter AI with RISC-V vector core from early 2019*(See Remarks). Andes later unveiled the AndesCore™ NX27V, marking a significant milestone as the industry’s first commercial RISC-V vector processor core with the capability of generating up to 4 512-bit vector (VLEN) results per cycle, at the end of 2019. It immediately attracted the attention of worldwide SoC design teams working on AI accelerators, and has landed over a dozen datacenter AI projects. Since then, the RISC-V vector processor cores have become the choice for ML and AI chip vendors.

With the goal to further raise the compute density, the AX45MPV extends the capabilities of the dual-issue 8-stage pipeline, Linux support and multicore of the AX45MP with the powerful vector processing unit inherited and enhanced from its predecessor, the NX27V. While the AX45MPV is essentially a Linux application processor with datacenter grade AI capabilities, its support for Linux and multicore can be left out to form an efficient and powerful compute processor in processing elements (PEs) of a large compute array.  The dual-issue capability combined with up to 6 1024-bit vector (VLEN) results per cycle in the AX45MPV can provide more than 3X performance comparing with its predecessor. To fully exploit its higher computation power, the AX45MPV offers two 1024-bit memory interfaces. The new high-bandwidth vector local memory (HVM) option provides 1 or 2 HVM bank ports, ideal for vector loads/stores, and an external DMA engine to move chunks of data in the background through an AXI-based HVM Access Port. For computation tasks requiring an integrated coprocessor control along with data transfer, the versatile Andes Streaming Port (ASP) available since the first Andes vector processor is the best solution.  By combining the ASP and the HVM ports, the processor effectively doubles its memory bandwidth by, say, being able to load 2 vector data per cycle. The AX45MPV also supports the latest ACE (Andes Custom Extension™), which facilitates customers to create their own RISC-V styled vector instructions.  For example, ACE can be used to accelerate nonlinear math functions such as SoftMax on Transformer AI.

“Andes has been serving datacenter AI customers since 2019 with RISC-V Vector architecture and has accumulated rich experience. Equipped with the powerful 1024-bit vector unit, efficient support of multicore and Linux, and versatile configurations, the third generation of Andes vector processors AX45MPV is specially tailored for Large Language Models (LLMs). With the surge of generative AI applications in 2023, we see the AX45MPV taking the center stage in AI and Machine Learning segments beyond the Cloud.”, said Dr. Charlie Su, President and CTO of Andes Technology.

Some customers from Asia and North America have already licensed the AX45MPV, and more are evaluating it. Their applications cover a wide range from the cloud to the edge. The AX45MPV standard product package, without Linux support, is available immediately. Its advanced product package will come with Linux support and will be available in Q4 2023.

 

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! ! 

*Remarks: MTIA: First Generation Silicon Targeting Meta’s Recommendation Systems, ISCA ’23: Proceedings of the 50th Annual International Symposium on Computer Architecture, June 2023

Continue ReadingAndes Announces General Availability of the New AndesCore™ RISC-V Multicore Vector Processor AX45MPV

GOWIN Semiconductor & Andes Technology Corp. Announce The First RISC-V CPU and Subsystem Ever Embedded 22nm SoC FPGA

GOWIN Is Offering the Andes A25 RISC-V CPU IP and AE350 Subsystem
As Instantiated Hard Cores in Its GW5AST-138 FPGA

San Jose, CA – Aug. 29, 2023 – Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, is thrilled to announce that its AndesCore™ A25 RISC-V CPU IP and AE350 peripheral subsystem is hardened and embedded in the GW5AST-138 FPGA chip from GOWIN Semiconductor, the world’s fastest growing FPGA company. This integration, one of the first complete RISC-V microcontrollers in an FPGA, provides designers the A25 processor power and the peripherals most processors require without consuming any FPGA resources. Thus, the hardware team can populate the FPGA with their value-added design while the software team can concurrently create application code based on the rich RISC-V ecosystem.

“Andes is committed to delivering cutting-edge RISC-V technologies allowing developers to create innovative and efficient solutions. The integration of the A25 RISC-V CPU and AE350 peripheral subsystem as a hard core in GOWIN Semiconductor’s GW5AST-138 FPGA marks a significant milestone in achieving this vision,” said Andes North America VP of Sales, Vivien Lin.  “This represents a significant milestone for the RISC-V architecture as it provides our joint customers a versatile hardware development platform to create, debug, and verify their ultimate SoC design before committing their netlist for silicon fabrication. For customers not requiring an SoC, it will enable a complete RISC-V computer ready to drive their end applications.”

“In the Arora V family, we incorporate the peripherals that a RISC-V CPU typically requires in hard instantiations,” says GOWIN’s Sr. Director of Solution Development, Jim Gao. “We included a fully controllable high-speed SerDes for communication, video aggregation, and AI computing acceleration applications that demand very high data rates. Other instantiated functions include Block RAM modules supporting ECC error correction, high-performance multiple voltage GPIO, and high accuracy clock architecture. These hard functions save the FPGA programmable fabric of up 138K LUT’s for the designers’ unique logic implementation.”

About the RISC-V Based GW5AST-138 FPGA:
The AndesCore™ A25 hard core, running at 400MHz, supports the RISC-V P-extension DSP/SIMD ISA (draft), single- and double-precision floating point and bit-manipulation instructions, and MMU for Linux based applications. The AE350 AXI/AHB-based platform comes with level-one memories, interrupt controller, debug module, AXI and AHB Bus Matrix Controller, AXI-to-AHB Bridge and a collection of fundamental AHB/APB bus IP components pre-integrated together as a system design. DDR3 controller and SPI-Flash controller in the FPGA fabric back up the A25’s 32KByte I-Cache and D-Cache after cache misses. Off chip DDR3 provides data memory, SPI-Flash contains the A25’s instruction memory (codes copied from SPI-Flash into DDR3 and Cache upon boot-up).  Besides hard instantiated functions, the GOWIN GW5AST-138 FPGA fabric affords 138K LUTs for custom design implementation.  GOWIN EDA provides an easy-to-use FPGA hardware development environment for the Arora V.  The environment supports multiple RTL-based programming languages, synthesis, placement and routing, bitstream generation and download, power analysis and in-device logic analyzer.

GOWIN PR

Price & Availability
The GW5AST-138 FPGA with SDK with GOWIN_V1.9.9 Beta-3 will be available August 18 through distribution.

About GOWIN Semiconductor Corp.
Founded in 2014, GOWIN Semiconductor Corp., headquartered with major R&D in China, has the vision to accelerate customer innovation worldwide with our programmable solutions. We focus on optimizing our products and removing barriers for customers using programmable logic devices. Our commitment to technology and quality enables customers to reduce the total cost of ownership from using FPGA on their production boards. Our offerings include a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits. We strive to serve customers in the consumer, industrial, communication, medical, and automotive markets worldwide.

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly listed company  (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! 

Continue ReadingGOWIN Semiconductor & Andes Technology Corp. Announce The First RISC-V CPU and Subsystem Ever Embedded 22nm SoC FPGA

Andes Technology and TetraMem Collaborate to Build Groundbreaking AI Accelerator Chip with Analog In-Memory Computing

San Jose, CA – Aug 10, 2023 – Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, and TetraMem Inc, a pioneer in analog memristor technology and in-memory computing, are proud to announce a strategic partnership aimed at delivering a fast, highly efficient, AI inference chip that will revolutionize the landscape of artificial intelligence and edge computing.

The convergence of AI and edge computing has become a driving force behind the advancement of numerous industries, including autonomous vehicles, smart cities, healthcare, cybersecurity, and entertainment. Recognizing the immense potential of this market, TetraMem has licensed the powerful Andes RISC-V NX27V vector CPU, combined with ACE (Andes Custom ExtensionTM) to create a cutting-edge solution that addresses the challenges of AI processing in power-constrained environments.

The centerpiece of this collaboration is the fusion of Andes’ high-performance RISC-V Vector CPU with TetraMem’s revolutionary compute memristor – an analog RRAM – in-memory computing architecture through ACE to enable tight coupling for the best performance. This unprecedented combination amplifies the strengths of both companies, resulting in blazingly fast, energy-efficient AI inference that surpasses the limitations of traditional computing approaches –  transcending “memory wall” and “end of Moore’s Law” constraints.

Features of the AI Accelerator Chip:
1. RISC-V Vector CPU Excellence: Andes RISC-V Vector CPU cores are known for their exceptional performance, efficiency, and configurability, making them ideal for a wide range of AI and edge computing applications. The addition of Andes powerful vector processor brings unparalleled performance capabilities to the accelerator chip.

2. Analog In-Memory Computing Prowess: TetraMem’s unique, analog in-memory computing technology empowers the chip with massively parallel VMM computation without data movement, mitigating the energy overhead of conventional architectures as confirmed in TetraMem’s first commercially manufactured demonstration chip.

3. Energy-Efficient AI Acceleration: The joint effort aims to create a chip that is not only powerful but improves energy-efficient by at least an order of magnitude. By optimizing computations and eliminating transfer of weight data, the planned chip will significantly extend the battery life of edge devices and impose a near-zero impact on thermal budgets.

4. Flexible and Scalable: The AI accelerator chip will be designed from 22nm and beyond, to 7nm and below in the future, with versatility and scalability in mind for easy integration into various AI-powered products and applications. This adaptability ensures broad industry applicability. The TetraMem founding team has demonstrated scalability of the compute memristor to 2nm and below, ensuring a roadmap to future-proof solutions.

Mr. Frankwell Lin, Chairman and CEO of Andes Technology, expressed his enthusiasm for the partnership, saying, “Our collaboration with TetraMem represents a significant milestone in the advancement of AI accelerators. By combining Andes’ world-class RISC-V vector processing technology with TetraMem’s groundbreaking analog in-memory computing, we are poised to deliver a revolutionary solution that will empower the next generation of AI applications.”

Dr. Glenn Ning Ge, CEO of TetraMem Inc,, echoed this sentiment, stating, “TetraMem’s analog-RRAM-based in-memory computing technology changes the physics of how AI computations are performed, launching a new era in computing. Working hand in hand with Andes, we are confident that our joint AI accelerator chip will set a new standard for AI processing in terms of speed and energy efficiency.”

Tetramem anticipates unveiling the AI accelerator chip and making engineering samples and development kits for the new 22nm “TetraMem MX Series” chip available to the public by the second half of 2024. The partnership between Andes and TetraMem signifies a major leap forward in the field of AI hardware, promising to unlock unprecedented possibilities for AI innovations.

For more information about Andes Technology and TetraMem Technologies, please visit their respective websites at www.andestech.com and www.tetramem.com.


About Andes Technology

Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

About TetraMem Inc
Founded in 2018 by a team of world-class experts, TetraMem is poised to deliver the industry’s most disruptive in-memory computing (IMC) technology for edge applications. The TetraMem team brings together complementary skill sets and technological know-how with 34 patents granted to date spanning materials science, device, circuit design, architecture, and application, as well as a patented six-dimension co-design methodology. TetraMem is the world’s only company to produce a high bit-density multi-level memristor-based accelerator in a commercial foundry, with the technology featured in the March 30, 2023 edition of the journal, Nature. This groundbreaking technology enables memory-based computation, eliminating weight-data movement, substantially improving the energy efficiency and performance of AI and machine learning workloads compared to digital technologies, with scalability well beyond the limits of competing analog technologies. For more information, please visit https://www.tetramem.com. Follow TetraMem on LinkedIn.

Continue ReadingAndes Technology and TetraMem Collaborate to Build Groundbreaking AI Accelerator Chip with Analog In-Memory Computing

Terapines ZCC Toolchain Fully Supports Andes RISC-V Processors

Wuhan, China – July 31, 2023 – Terapines Technology, an innovative provider of software/hardware co-design solutions announces the full support for Andes RISC-V processors lineup in the Terapines ZCC toolchain. The ZCC toolchain delivers proven performance gains across multiple end markets, including embedded systems, high-performance computing, and AI. Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, has been instrumental in driving RISC-V into the mainstream. Recently, Terapines Technology has joined RISC-V International as a Strategic Member, enabling closer collaboration between these two companies and the overall RISC-V community.

The full support of ZCC toolchain for AndeStar™ V5 Instruction Set Architecture will allow Andes and its silicon partners to achieve higher code density and performance for MCU and SoC products built on the V5 architecture. It opens the door to optimized RISC-V implementations across a wider range of applications.

The benchmark results demonstrate the ZCC toolchain’s ability to optimize the system performance versus LLVM from AndeSight™ IDE. Based on AndesCore™ AX45 CPU, ZCC achieved a 6% boost over the baseline on CoreMark score, as well as an 18.9% performance improvement and 11.8% better code density on Embench-IoT (-O3). With -Os optimization, Embench-IoT attained a 10% code density gain and 9.1% faster performance.

On the industry-standard SPECInt2006 benchmark, ZCC delivered a 30% lower dynamic instruction count compared to open-source LLVM 16.0 on a RV64GCBV RISC-V processor. It also achieved a 13% lower dynamic instruction count on a RV64GCB RISC-V processor.

These gains showcase the potential of the ZCC toolchain to help engineers maximize efficiency and real-world speedup across a wide variety of RISC-V implementations.

Benchmark results also highlight the powerful auto-vectorization capabilities of ZCC toolchain for AI chip development. ZCC achieved up to 91x higher performance versus open-source compilers on popular computing kernel functions. In some cases, the auto-vectorized output even matched or exceeded hand-optimized assemblies in both performance and efficiency.

These exceptional auto-vectorization results mean ZCC can substantially accelerate AI chip design and lower software maintenance costs. By reducing the need for time-consuming manual optimization of computational kernels, ZCC provides a streamlined path to deploying high-throughput AI accelerators.

“Full support for AndeStar™ V5 ISA in the ZCC toolchain is just the starting point of our collaboration with Andes,” said Hualin Wu, CTO of Terapines Technology. “We look forward to deepening our partnership to further boost the performance and efficiency of Andes RISC-V processors. Beyond the toolchain, Terapines will provide Andes’ customers with access to our full suite of co-design tools and virtual prototype simulators. This will enable rapid and cost-effective design flow of competitive RISC-V chips optimized for their target applications.”

“This collaboration between Terapines and Andes to optimize RISC-V processor performance and code density will greatly benefit our mutual customers,” said Dr. Charlie Su, President and CTO of Andes Technology. “As RISC-V continues its rapid growth, expanding the ecosystem with professional tools like ZCC is crucial for ensuring customer product competitiveness. We look forward to broadening our collaboration to equip designers with the best-in-class solutions needed to maximize the potential of RISC-V.”

About Terapines
Founded in late 2019, Terapines Technology specializes in developing RISC-V software/hardware co-design toolchain. With optimized compilers and simulators as core technologies, Terapines offers products and solutions across four key areas: software/hardware co-design and co-verification, functional safety checker, DSA and embedded development, and ROS operating systems. To learn more about Terapines’ innovative RISC-V solutions, follow our WeChat official account or visit https://www.terapines.com

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) , a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, with processor integrating vector processor and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com.  Follow Andes on LinkedIn , Twitter, Bilibili  and YouTube!

Continue ReadingTerapines ZCC Toolchain Fully Supports Andes RISC-V Processors

Andes Technology Unveils the Annual ANDES RISC-V CON, Scheduled for June 27th at the San Jose Airport DoubleTree Hotel

RISC-V: Redefining AI’s Future in Automotive, Data Center, Communications, and IoT

San Jose, CA — June 27, 2023 — Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, announces its annual ANDES RISC-V CON on June 27th at the San Jose Airport DoubleTree Hotel. In 2023, the reputable conference in the RISC-V field will focus on the theme of “RISC-V: Redefining AI’s Future in Automotive, Data Center, Communications, and IoT.” The event serves as a nexus for eminent experts, accomplished researchers, and prominent industry leaders to engage in insightful discussions regarding the latest breakthroughs in RISC-V, and the total number of registered attendees has exceeded 500.

The ANDES RISC-V CON offers an exceptional program featuring insightful presentations from Philipp Tomsich, Chair, RISC-V Software Committee; Sanjay Dave,  TSMC; Barna Ibrahim, Vice Chair, RISE Project; Adil Kidwai, EdgeQ; Larry Lapides, Imperas; Chuck Brokish, Green Hills; Shawn Prestridge, IAR. The event also includes informative technical panel: Open-Source Is Transforming AI And Hardware, involving key partners in the RISC-V ecosystem. The moderator is Dylan Patel, Chief Analyst, SemiAnalysis and panelists are Andrew Feldman, Cerebras; Horace He, Meta, Charlie Cheng, Polyhedron, Raja Khoduri, Stealth Startup and Jim Keller, Tenstorrent. Their discussion will focus on the future of AI and hardware through the lens of open-source.

The event will commence at 9:30 AM with a welcome address from Andes Technology‘s Chairman and CEO, Frankwell Lin. It will delve into the RISC-V trend and shed light on the significant contributions made by Andes in enabling the realization of the RISC-V community’s achievements. Furthermore, Dr. Charlie Su, President & CTO of Andes Technology will have the keynote “Firing on All Cylinders with Andes RISC-V Processors.” When RISC-V has been adopted in diverse applications from tiny MCUs, Linux-capable MPUs, 5G networking, enterprise storage to AI/ML accelerators with novel technologies such as compute-in-memory and photonics, the speech will give an overview of Andes RISC-V processor lineup and showcase examples of recently disclosed RISC-V applications powered by AndesCore™. In the afternoon session, Samuel Chiang, Deputy Director of Marketing of Andes Technology will also give a talk “Exploring Latest Andes RISC-V Products for Automotive and AIoT.” 

The exhibition held alongside the conference program will showcase an exciting range of technological advancements. Attendees will have the opportunity to explore the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; an AI development kit with a camera module from Canaan; the IT9836 TDDI demo board from ITE; the PC802SCB 5G small cell reference design from Picocom; Bluetooth development kit from Telink incorporating Andes RISC-V CPU IP. Besides, there are also global leading companies to have booths and demos in Andes RISC-V CON, including EdgeQ, Gowin, Green Hills, IAR, Imperas, Menta, QuickLogic, Rapid Silicon, RISE, Siemens, Tetramem and TSMC.

ANDES RISC-V CON serves as an excellent platform for RISC-V enthusiasts to engage in personalized conversations with the knowledgeable experts worldwide. Running from 9:30 AM to 5:00 PM, the conference program ensures a comprehensive experience that encompasses a lunch and a delightful evening reception. After the Q&A sessions following the final presentation, lucky participants will have a chance to win one of two Meta VR headset and one of two Beats Earbuds. The conference is free of charge and is available to qualified registrants, including design engineers, engineering managers, marketing professionals, and business development personnel.

To register, click https://www.eventbrite.com/e/2023-andes-risc-v-con-silicon-valley-registration-624048886017?aff=oddtdtcreator

If you can’t attend in person, the event will be livestreamed. E-mail jonahm@andestech.com for the Livestream link.

About ANDES RISC-V CON
ANDES RISC- V CON is the annual RISC-V technology forum of Andes Technology. In 2023, the San Jose session will be held in Doubletree by Hilton Hotel on June 27. The 2023 theme is “RISC-V: Redefining AI’s Future in Automotive, Data Center, Communications, and IoT.” It will introduce the flexible RISC-V that changes the face of emerging computing and share how Andes assists the RISC-V ecosystem in implementing multiple applications of innovative technology. Three popular application areas will be focused on: AI, automotive electronics, and RISC-V’s new field, Android. Many RISC-V ecosystem partners, including TSMC, are invited to give talks and on-site demonstrations. For free registration, please see the official website of Andes RISC-V CON: https://www.andestech.com/Andes_RISC-V_CON_2023_US/

About Andes Technology

Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Facebook, Twitter, Bilibili and YouTube! 

Continue ReadingAndes Technology Unveils the Annual ANDES RISC-V CON, Scheduled for June 27th at the San Jose Airport DoubleTree Hotel

Andes Technology Showcases Pioneering RISC-V CPU IP Solutions at RISC-V Summit Europe

 Discover the Future of CPU Technology and the RISE project at Andes’ Exhibition Display in Booth 14

Barcelona, Spain – June 5, 2023 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading provider of high efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, is pleased to announce its diamond sponsor participation in the prestigious RISC-V Summit Europe. This premier event, taking place from June 5 to 8, 2023 in Barcelona, Spain, will feature Andes as a key contributor, presenting a keynote speech, poster publication, and participation in an automotive panel discussion. Additionally, Andes will be showcasing its cutting-edge RISC-V CPU IP solutions at booth #14.

Join Dr. Charlie Su, President and CTO of Andes, as he delivers an engaging keynote titled “RISC-V is Firing on All Cylinders” on June 6 at 12:00 PM. Dr. Su will highlight the rapid adoption of RISC-V across a wide range of applications, from small microcontrollers to AI/ML accelerator systems in data centers. The keynote will provide examples of RISC-V applications and the corresponding solutions to support them and will also explore different approaches for matrix multiplication extension, enabling direct AI/ML acceleration with the RISC-V architecture. Furthermore, Dr. Charlie Su will contribute to a panel discussion on “Automotive/Embedded” on June 6 at 17:30 PM. Andes recently announced its new product line, AndesAIRE™, which offers highly efficient AI/ML solutions for edge and end-point inference. On, June 7, Warren Chen, Andes senior Technical Manager, Marketing, will give a demo presentation titled “Andes AI Runs Everywhere (AndesAIRE™) with DSP/Vector/NN Libraries and AndesClarity” in the demo theater on June 7 at 11:10 AM.

In addition, Andes will proudly showcase development boards with AndesCore-Embedded™ technology at booth #14. These boards include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; an AI development kit with a camera module from Canaan; the IT9836 TDDI demo board from ITE; and the PC802SCB 5G small cell reference design from Picocom.

You can learn more about the RISC-V Software Ecosystem (RISE) project on Andes booth #14. “Andes is proud to be part of the newly launched RISE Project, a new open source initiative to accelerate the development of software for RISC-V across a variety of market segments. Hosted by Linux Foundation Europe, RISE will support the global standards activities and achievements of RISC-V International,” said Dr. Charlie Su, CTO and President of Andes Technology and a Director of the RISE Governing Board. Please visit the RISE website for how to join and other information.

This event presents a valuable opportunity for RISC-V enthusiasts to engage in one-on-one discussions with Andes experts, enabling deeper exploration of RISC-V solutions. We invite you to visit booth #14 at the RISC-V Summit Europe and experience live demonstrations of our leading-edge CPU IP technology.

Details of Andes’ sessions during the RISC-V Summit Europe are as follows:

Tuesday, June 6,

  • 12:00 – 12:15 PM: Keynote “RISC-V is Firing on All Cylinders” by Dr. Charlie Su, President and CTO
  • 17:30 – 18:30 PM: Automotive/Embedded Panel by Dr. Charlie Su, President and CTO

Wednesday, June 7,

  • 11:10 – 11:30 AM: Demo Talk “Andes AI Runs Everywhere with DSP/ Vector/ NN Libraries and AndesClarity” by Warren Chen, Senior Technical Manager, Marketing

For more information, please visit the RISC-V Summit Europe website.

About Andes RISC-V CON
Andes RISC- V CON is the annual RISC-V technology forum of Andes Technology. In 2023, the San Jose session will be held in Doubletree By Hilton Hotel on June 27. The 2023 theme is “RISC-V: Redefining AI’s Future In Automotive, Data Center, Communications, And IoT”. It will introduce the flexible RISC-V that changes the face of emerging computing and share how Andes assists the RISC-V ecosystem in implementing multiple applications of innovative technology. Three popular application areas will be focused on: AI, automotive electronics, and RISC-V’s new field, Android. Many RISC-V ecosystem partners, including TSMC, are invited to give talks and on-site demonstrations. For free registration, please see the official website of Andes RISC-V CON: https://www.andestech.com/Andes_RISC-V_CON_2023_US/

About Andes Technology

Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn、Facebook、Weibo、Twitter、Bilibili and YouTube! 


Continue ReadingAndes Technology Showcases Pioneering RISC-V CPU IP Solutions at RISC-V Summit Europe