Andes Technology: Cultivating Academic Collaboration for Over a Decade with Sustainable Spirit

【Mar. 12, 2024 -Hsinchu, Taiwan】Andes Technology (TWSE: 6533), since the first agreement signed with National Chiao Tung University in 2010, has actively keeping engaged in industry-academia collaboration. Collaborating with universities across Europe, Asia, and US over a decade, Andes has signed agreements with over 80 universities worldwide.

Andes provides CPU IP Cores licensing, AndeSight™ development tools, software, and hardware/software development platforms to facilitate industry-academia collaboration. From the early self-developed V3 series to the fifth-generation V5 RISC-V processor series starting2018, Andes has continuously collaborated with globally renowned institutions for research and product licensing. Over a decade, Andes has actively contributed various hardware/software resources, and established joint laboratories with universities and research institutions. The total number of agreements signed with universities worldwide has exceeded 150.

Recently, as the growing focus on ESG indicators, social responsibility emphasizes that companies must not only prioritize profits and shareholder interests but also uphold responsibilities to employees, society, and the environment. With its long-term commitment to academia, Andes has contributed to campus activities and supported young professionals through industry-academia collaboration projects. These initiatives include providing advanced RISC-V core processing unit IP, System-on-Chip (SoC) technology, comprehensive training materials, professional teaching courses, organizing lectures, seminars, conducting unique certification exams, and hosting the creative Andes Cup competition, among other technical services.

RISC-V, well-known for its open, compact, modular, and extensible instruction set, has garnered significant attention in the market, with widespread adoption in Asia-Pacific markets, including Taiwan, Japan, Korea, China, as well as in Europe and the United States. Among the 150+ school agreements signed, Andes provides the latest RISC-V development tools, such as AndeSight™, RISC-V processor debuggers, project implementation examples, verification, and algorithm performance analysis. In terms of curriculum instruction, National Tsing Hua University (NTHU) was among the first to use Andes’ RISC-V development tools in computer architecture and compiler design courses. NTHU also acquired RISC-V FPGA development platforms Corvette F1 and Corvette T1 for instructional experiments and student projects. Over the past two years, there has been a steady increase in enrollment, with over 400 students using the tools annually at NTHU. More than ten universities have incorporated Andes tools and platforms into their teaching, accumulating over 5,000 students in the last five years.

In the realm of processor IP licensing projects, there have been a total of more than a dozen RISC-V projects licensed. These projects span various applications, including biomedical, security, Artificial Intelligence (AI), Internet of Things (IoT), and machine learning (ML), with a particular focus on AI research. The licensed processors range from the entry-level processor N22, the 5-stage pipeline processor N25, to the vector processor NX27V and the high-end multicore processor AX45MP. Some research teams obtained licenses for the AndesCore™ V5 RISC-V core and successfully completed tape-out and chip testing at the Taiwan Semiconductor Research Institute of NARLabs. Furthermore, some research teams, based on academic research outcomes, have established startup companies, with updated commercial agreement re-signed, transforming academic licenses into commercial licenses to turn research results into commercial chip for the market.

The Andes Certified Engineer Test (ACET™ Program) is designed to help students obtain certifications and has been recognized by various educational institutions. Students who pass the exam not only meet graduation requirements but also acquire industry skills such as programming, practical operations, and reading product documentation. By integrating these skills with the school’s programming language courses and embedded platform operations, students gain insights into the industry’s product development process and gain early exposure to engineering work. Recently, the platform used for certification exam has transitioned to the RISC-V platform, with a steady growth in registrations, accumulating 2,000 applicants over thirteen years. To encourage more students to participate in RISC-V development, Andes Technology also organizes competition campaigns with substantial cash prizes. The second annual Andes Cup held in 2023, themed “The Great Advance of Artificial Intelligence,” attracted 43 teams from 17 schools.

Frankwell Lin, Chairman and CEO of Andes Technology, stated, “Andes Technology has integrated ESG into annual goals by supporting schools with resources like AndesCore™ and AndeSight™ for research and tech development. This initiative helps cultivate students with practical skills and provides assistance to universities participating in collaborative projects. Through diverse industry-academia cooperation programs, Andes Technology is committed to achieving the dual goals of talent cultivation and industry cooperation, in order to give back to society.”


About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533SIN: US03420C2089ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety, and/or multicore capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com.
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Andes and MachineWare Collaborate on Early RISC-V Software Development for AndesCore™ AX45MPV

Aachen, Germany and Hsinchu, Taiwan, February 27th 2024
MachineWare GmbH and Andes Technology (TWSE:6533), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announce an exciting new chapter in their collaboration, marked by a strategic partnership. This synergistic alliance is geared towards the highly innovative AndesCoreAX45MPV, a cutting-edge multi-core RISC-V vector processor tailored for AI workload acceleration and the application level. In this joint effort, MachineWare lends its support by seamlessly integrating the AX45MPV into their SIM-V high-performance simulation solution. This integration proves invaluable for software developers, enabling them to efficiently handle intricate AI and Linux stack related workloads. The result is a platform that streamlines development, testing, and software verification well in advance of physical prototypes emerging from the fabrication process. This partnership underscores the mutual commitment of MachineWare and Andes Technology to advancing processor technology.

Introducing SIM-V, an offering from MachineWare that holds immense value for developers in the RISC-V landscape. With SIM-V, developers gain the power to thoroughly test and verify their RISC-V-based systems and software applications long before first prototypes are back from the fab. At its core, SIM-V provides a fast Instruction Set Simulator (ISS) that supports all RISC-V standard extensions. One of SIM-V‘s notable strengths is its user-friendly customizability. Through a straightforward extension SDK, developers can swiftly integrate custom instructions, registers, and other elements into the simulator to get instant feedback on their design choices. What makes SIM-V truly special is its SystemC TLM-2.0 integration. This unique combination empowers users to seamlessly introduce their IP models into full system simulation environments, enhancing the versatility of the platform.

The AndesCore™ AX45MPV is a 64-bit 8-stage dual-issue multicore RISC-V vector processor. It incorporates RISC-V GCBP* (*P is a draft version) extensions, and supports SMP Linux with MMU (Memory Management Unit) and up to 48-bit virtual addresses. In addition, it can be configured to up to eight cores with a cache coherence manager and up to 8MB shared L2 cache memory in a cluster. The Vector Processing Unit (VPU) of the AX45MPV implements RISC-V Vector Extension (RVV) version 1.0. It supports configurations of up to 1024-bit vector width (VLEN) and datapath width (DLEN). The AX45MPV is excellent for computations involving large arrays of data such as computer vision, digital signal processing, image processing, machine/deep learning, and scientific computing.

Figure 1: Invoking SIM-V with the AX45MPV configuration.

“We are delighted to join forces with Andes to support the AX45MPV processor in SIM-V,” said Lukas Jünger, Managing Director at MachineWare. “The incorporation of the AX45MPV model enables our common customers to develop RISC-V Linux and AI software stacks and verify their functionality in minutes. This will eliminate bugs and elevate software quality all the while making the overall development process more efficient.”

“Andes’ collaboration with MachineWare is consistent with our continuous effort to broaden RISC-V ecosystem for easy adoption of high-performance simulation tools,” said Samuel Chiang, deputy marketing director of Andes Technology. “We are excited to come together with MachineWare to drive the expansion of the RISC-V ecosystem. And we believe RISC-V’s instruction set architecture will increase innovation and has the potential to transform the AI market.”

About MachineWare GmbH
Founded in 2022 in Aachen, Germany, MachineWare leverages decades of experience in system level simulation and high-performance simulation tooling. Visit https://www.machineware.de/ for more details.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, automotive and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com . Follow Andes on LinkedInTwitterBilibili and YouTube!

About ANDES RISC-V CON
ANDES RISC- V CON is the annual RISC-V technology forum of Andes Technology. In 2024, the Hsinchu session will be held at Amazing Hall Yufeng on March 28; the Shanghai session will be held at DoubleTree by Hilton Hotel Shanghai – Pudong on April 9; the Shenzhen session will be held at Grand Mercure Shenzhen Oriental Ginza Hotel on April 11. The theme of this year is “ANDES RISC-V CON: Deep Dive into Automotive/ AI/ Application Processors and Security Trends.” It will introduce the flexible RISC-V that revolutionizes emerging applications and share Andes latest breakthroughs and innovations in RISC-V. Four popular applications will be focused on: AI, automotive electronics, security and RISC-V’s new field, application processor. Many RISC-V ecosystem partners, including TSMC, are invited to deliver talks and on-site demonstrations.

For more event details and free registration, please visit the official website of the events:


About RISC-V
The RISC-V open architecture ISA is under the governance of RISC-V International. Visit https://riscv.org for more details.


MachineWare Contact
Lukas Jünger, Managing Director
E-mail: lukas@mwa.re

Andes Technology Contact
Jonah McLeod, Press Contact, Andes Technology
Tel: +1-510-449-8634
E-mail: Jonahm@andestech.com

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Andes Technology to Exhibit Groundbreaking RISC-V Solutions for AI and Automotive at RISC-V Summit North America 2023

Discover the cutting-edge insights from Andes’ presentations and explore live demonstrations of CPU IP technology at Booth #D4 and get your opportunity to seize lucky draw prizes, including mobile phones!

SAN JOSE, CA – Oct. 31, 2023 – Andes Technology Corporation (TWSE: 6533), a leading provider of high efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, announces its significant role as the diamond sponsor in RISC-V Summit North America, the prestigious annual event held from November 6 to 8, 2023 in Santa Clara. As a key contributor, Andes will deliver a keynote speech about AI/ML SoC solutions based on RISC-V and the latest on Andes RISC-V processors to enable them. Andes will also address three presentations and two demo talks focused on AI/ML solutions, automotive-grade IP, IOPMP, RISC-V vector technology and more. During the event, Andes will showcase its state-of-the-art RISC-V CPU IP offerings at booth #D4.

Andes President and CTO, Dr. Charlie Su, will present why RISC-V is a perfect solution to bring intelligence everywhere and introduce Andes product portfolio in the keynote speech “Taking RISC-V Intelligence Everywhere” on November 8 at 9:55 AM. Dr. Paul Ku, Deputy Director of Andes and chair of IOPMP task group, will give an update of IOPMP spec on November 6 at 14:55 PM. Chun-Nan Ke, Senior Technical Manager, will explore the Andes proposal for RISC-V matrix multiplication instructions which enhance significant performance for AI applications in his presentation “Advancing AI Computing with Optimized Matrix Multiplication Techniques with RISC-V CPU” on November 7 at 12:10 PM. Furthermore, Dr. Heng-Kuan Lee, Senior Manager, will discuss how to enhance efficiency and accuracy of computations in transformer models in “Enhancing Transformers: Accelerating Nonlinear Function Computation on RISC-V Vector Processor” on November 7 at 15:15 PM. Lastly, Hubert Chung, FAE Manager, will deliver a demo talk “AI Solution – AndesAIRE, including HW and SW” on November 7 at 12:55 PM . Marvin Chao, Director of Solution Architect, will give the other demo talk “Andes Technology RISC-V Functional Safety Solutions” on November 7 from 11:10 to 11:20 AM at the demo theater.

In addition, Andes will proudly display development boards integrated with Andes-Embedded™ technology at the Developer Zone. These boards include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; high-performance industrial-grade microcontrollers from HPMicro; one of the first complete RISC-V microcontrollers with an embedded FPGA from Gowin; and an Arduino-compatible development board based on a wireless SoC from Andes. Seize the opportunity to understand how customers are working with Andes products for various applications by visiting the Developer Zone. Also, Andes will announce its new safety-enhanced core, D25F-SE, at the Launchpad session.

Besides presentations and live demo, RISC-V Board of Director and Andes CEO, Frankwell Lin, will join the Media Panel Luncheon RISC-V is HERE: Future Outlook with Invested RISC-V Leaders” on November 7 at 13:00 PM. Join the discussion to discover the remarkable progress in the RISC-V ecosystem across diverse applications and witness how RISC-V is empowering companies with advanced design flexibility.

This event presents a valuable opportunity for RISC-V enthusiasts to reserve one-on-one discussion with Andes experts to explore RISC-V solutions in-depth. Andes invites you to visit booth #D4 at the RISC-V Summit and experience live demonstrations of its leading-edge CPU IP technology. Stop by Andes’ booth for a chance to win fantastic prizes, including mobile phones!

Details of Andes’ sessions during the RISC-V Summit are outlined below:

  • November 6 (Member Day),
    • 14:55-15:20 PM: Presentation “IOPMP Update” by Dr. Paul Ku, Deputy Technical Director
  • November 7 (Day 1),
    • 12:10-12:30 PM: Presentation “Advancing AI Computing with Optimized Matrix Multiplication Techniques with RISC-V CPU” by Chun-Nan Ke, Senior Technical Manager, and Dr. Heng-Kuan Lee, Senior Manager
    • 13:00-13:55 PM: Media Panel Luncheon “RISC-V is HERE: Future Outlook with Invested RISC-V Leaders” by Frankwell Lin, Chairman and CEO
    • 12:55-13:05 PM: Demo “AI Solution – AndesAIRE, including HW and SW” by Hubert Chung, FAE Manager
    • 15:15-15:35 PM: Presentation “Enhancing Transformers: Accelerating Nonlinear Function Computation on RISC-V Vector Processor” by Dr. Heng-Kuan Lee, Senior Manager, and Simon Wang, Senior Technical Manager
  • November 8 (Day 2),
    • 9:55-10:10 AM: Keynote “Taking RISC-V Intelligence Everywhere” by Charlie Su, CTO and President
    • 11:10-11:20 AM: Demo “Andes Technology RISC-V Functional Safety Solutions” by Marvin Chao, Director of Solution Architect

For more information, please visit the RISC-V Summit website.

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Facebook, Weibo, Twitter, Bilibili and YouTube

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