Join Andes at RISC-V Summit; Learn the Only ISO 26262 Fully-Compliant RISC-V CPU, the Latest Multicore 4-Way Out-Of-Order Processor & the Multicore 1024-bit Vector Processor

Visit Andes’ Exhibition Hall Display in Booth D4 to View Live Demonstrations of its Leading-Edge CPU IP Technology

SAN JOSE, CA – December 7, 2022 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announces its diamond sponsor participation in the RISC-V Summit, the premier annual event held from December 13 to 14, 2022 in San Jose McEnery Convention Center. The company will contribute three presentations and will also demonstrate its cutting-edge RISC-V CPU IP solutions at booth #D4. 

Andes President and CTO, Dr. Charlie Su, will present a wide range of RISC-V applications and introduce Andes’ new product lines which benefits the industry in the keynote speech “Expanding the RISC-V Horizon and Beyond” on December 14 at 10:00 AM. John Min, Director of Solution Engineering, Andes Technology USA, will introduce multiple new processors optimized for new application areas in his presentation “Future is Sideways – Not Only Up and Right” on December 13 at 4:45 PM. Furthermore, Hubert Chung, FAE Manager of Andes Technology, will give a talk on “Andes AI solutions: AndesClarity and NN/Vector Libraries” on December 14 at 1:00 PM at Demo Theater. 

In these informative speeches, the audience will get to learn the leading AndesCore™ RISC-V processor IP solutions. They include the recently announced N25F-SE, the industry’s first and only ISO 26262 fully-compliant RISC-V CPU; just announced AX65, a multicore 4-way out-of-order superscalar processor; the new AX45MPV, the leading-edge Linux multicore 1024-bit vector processor; and the new D23, the new-generation compact, versatile, secured core for IoT applications.

Andes will showcase the development boards with AndesCore ™embedded at our booth, including MPU development board from Renesas, AI development kit with camera module from Canaan, high-performance industrial-grade microcontrollers from HPMicro, Bluetooth development kit from Telink, IT9836 TDDI demo board from ITE and PC802SCB 5G small cell reference design from Picocom.

Besides presentations and live demo, Andes will join the RISC-V Member Day which kicks off the whole event on December 12. Andes CEO, Frankwell Lin, along with Andes President and CTO, Dr. Charlie Su will be interviewed during the Future Watch press conference and make a 25-minute talk about corporate updates and latest products. In addition, Andes is sponsoring the Onsite Attendee Reception in the main exhibition hall on December 13 at 5:10 PM. Join fellow attendees and enjoy refreshments at the end of the first RISC-V Summit day of presentations!

Please don’t forget to visit Andes booth #D4 and participate in the lucky draw to win an Andes Embedded Razor Gaming Headset! It’s a good opportunity for RISC-V enthusiasts to reserve one-on-one discussion with Andes experts to explore RISC-V solutions in further depth.

Details of Andes’ sessions during the RISC-V Summit are as follows:

 Monday, December 12,

•       11:00 – 11:25 AM: Future Watch (Press Conference)

Tuesday, December 13,

•       4:45 – 5:10 PM: Presentation “Future is Sideways – Not Only Up and Right” by John Min, Director of Solution Engineering

•       5:10 – 8:30 PM: Onsite Attendee Reception

Wednesday, December 14,

•       7:30 – 8:45 AM: RISC-V Influencers Breakfast

•       10:00 – 10:20 AM: Keynote “Expanding the RISC-V Horizon and Beyond” by Dr.Charlie Su, President and CTO

•       1:00 – 1:40 PM: Demo “AI Solution Including AndesClarity and NN/Vector Libraries” by Hubert Chung, FAE Manager

For more information, please visit the RISC-V Summit website.

About Andes Technology Corp.

Seventeen years in business and a Founding Premier member of RISC-V International, Andes is publicly listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube! 

Continue ReadingJoin Andes at RISC-V Summit; Learn the Only ISO 26262 Fully-Compliant RISC-V CPU, the Latest Multicore 4-Way Out-Of-Order Processor & the Multicore 1024-bit Vector Processor

Andes Announces RISC-V Multicore 1024-bit Vector Processor: AX45MPV

Vector Processing is brought to the Award Winning AndesCore™ 45-Series

SAN JOSE, CA – December 7, 2022 – Andes Technology Corporation  (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today proudly announces the new member of popular AndesCore™ 45-Series, the AX45MPV with Linux multicore and 1024-bit vector processing capabilities. The AX45MPV targets the applications with large volumes of data such as datacenter AI inference and training, ADAS, AR/VR, computer vision, cryptography, and multimedia.

The AX45MPV inherits all the features of the AX45MP and leverages the 3-year field experience of the successful Andes vector processor NX27V. The AX45MP is a 64-bit 8-stage dual-issue multicore RISC-V processor. It incorporates RISC-V GCBP* extensions, and supports SMP Linux with MMU (Memory Management Unit) and up to 48-bit virtual addresses. In addition, it can be configured to up to eight cores with coherence manager and up to 8MB shared L2 cache memory in a cluster. The coherence manager ensures the data coherence of all L1 data caches and supports the optional IO coherence port. (*P is a draft version)

The Vector Processing Unit (VPU) of the AX45MPV implements RISC-V Vector Extension (RVV) version 1.0. It supports configurations of up to 1024-bit vector width (VLEN) and datapath width (DLEN). The VPU can dual-issue vector instructions to functional units, where instructions with all inputs ready can be executed simultaneously and can produce up to 6 x 1024-bit results every cycle. The data formats can be integer, fixed-point and floating point as well as Andes-extended data types optimized for AI representations. In addition, the vector load and store segment instructions can move multiple contiguous fields in memory to and from consecutive vector registers to allow efficient vector processing of video, audio/speech, complex numbers, and other data. Furthermore, the Andes Streaming Port (ASP), first available in the NX27V, is a dedicated command and data interface to move large amount of data between AX45MPV (scalar and vector) registers and an external accelerator. The command part of the RVV-aware ASP is user-defined with optional on-the-fly operations designed through the powerful Andes Custom Extension™ (ACE) framework.

“The AX45MPV multicore vector processor is another important milestone for Andes and RISC-V enthusiasts since our NX27V, the first RISC-V commercial vector processor and a very successful one announced 3 years ago,” said Andes Chairman and CEO, Frankwell Lin. “Some of our customers are looking for a Linux-capable multicore vector processor with faster data movement and computations. The versatile AX45MPV empowers our customers to fulfill their various demands for compute acceleration. It is exciting to see AX45MPV perfectly satisfy their expectations.”

“Multicore vector processors are designed for applications with high parallelism. The AX45MPV with outstanding scalar performance supports up to eight cores in one cluster with coherence manager and an optional L2 cache controller,” said Dr. Charlie Su, CTO and President of Andes. “Compared with the NX27V at its maximum VPU configuration, 512-bit VLEN and DLEN, the similarly-configured AX45MPV is expected to deliver 20%~40% higher performance for non-MAC dominated computation kernels while the AX45MPV with 1024-bit VLEN and DLEN can deliver 2x performance for MAC dominated kernels. The AX45MPV has being requested by customers whose applications need to process arrays of data with size over 1024 bits.”

The AX45MPV fully supports the AndeStar™ V5 architecture, which includes the latest RISC-V extensions and also Andes extended features such as PowerBrake and QuickNap™ for power saving; StackSafe™ for stack overflow/underflow protection; and CoDense™ for additional code density enhancement on top of RISC-V C-extension. Furthermore, the AX45MPV benefits from all existing Andes development tools for AX45MP and NX27V such as the AndeSight™ IDE and optimizing compilers, the Vector and Neural Network libraries, the intuitive AndesClarity™ pipeline visualizer and analyzer to help optimize performance-critical computation kernels, and Andes Custom Extension™ framework. It can also leverage the broader RISC-V ecosystem from security solutions to system level modeling, and hardware debug/trace subsystems.

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion since 2021 and continues to rise. In the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion.

For more information, please visit https://www.andestech.com/en/homepage

Follow Andes on Twitter, LinkedIn, YouTube and Facebook.

Continue ReadingAndes Announces RISC-V Multicore 1024-bit Vector Processor: AX45MPV

Andes Technology Unveils the AndesCore™ D23, a Feature-Rich, Low-Power and Highly-Secured Entry-Level RISC-V Processor

D23 Delivers the Industry Leading 4.13 Coremark/MHz with the Latest RISC-V ISA

SAN JOSE, California – December 7, 2022 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announces the details of the AndesCore™ D23, a new 3-stage 32-bit RISC-V CPU core, to target embedded processing and IoT applications that require low power and high efficiency in a small footprint. The D23 achieves the industrial leading performance of 4.13 Coremark/MHz among the similar level of cores, the worst-case operating frequency at 28nm of up to 800MHz, and the minimum usable configuration at 26K gates.

“The D23 is a new member of the Entry Series AndesCore™ with a small gate count and high performance-efficiency. In addition to RISC-V RV32GC extension including single/double precision FPU, it supports the recently ratified extensions such as bit manipulation (B) extension, scalar cryptography (K) extension, cache management operation (CMO) extension, code size reduction extension and the draft of packed SIMD/DSP extension. The packed SIMD extension together with Andes NN SDK, which includes TensorFlow Lite and Andes AI optimizer,  help customers to provide AI acceleration in a small package. It also deploys Core-Local Interrupt Controller (CLIC) which can service more than 1000 interrupts for fast interrupt response, interrupt prioritization and pre-emption, and Andes V5 extensions that includes StackSafe™ for hardware stack protection, CoDense™ for code size compression on top of the C extension, and PowerBrake for power management,” stated President and CTO, Dr. Charlie Su.  “Other advanced functions like instruction and data caches, memory soft error protection and Andes Custom Extension™ will be available too.”

Furthermore, the D23 packs many security features, such as enhanced and supervisor-mode Physical Memory Protection (ePMP/sPMP) to improve CPU core’s security level. The new scalar cryptography extension (K) provides instructions to accelerate AES encryption/decryption for network and data encryption and SHA256/512 instructions for digital signatures and certificates. The D23 also supports AndeSentry™, a security framework that enables open collaboration with our security partners to provide security solutions such as secure boot/debug and TEE. The D23 is perfect match for the new Matter IoT standard because its strong security features. The D23 gives designers the ability and flexibility to meet the demands for DSP processing, security, power, area and performance. Therefore, it can be used in many applications such as smart home appliances, wearables, AIoT devices and special purpose MCUs.

The D23 with most features will be available for early customer evaluation at Q1 2023, and its full features for general customer evaluation at Q3. Please contact Andes Sales for the details at sales@andestech.com.  

 

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes is publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube!   

Continue ReadingAndes Technology Unveils the AndesCore™ D23, a Feature-Rich, Low-Power and Highly-Secured Entry-Level RISC-V Processor

Andes Technology and Parasoft Collaborate to Provide Seamless Software Testing Tools for Automotive Functional Safety Applications

SAN JOSE, CA – December 7, 2022 – Andes Technology, a leading supplier of high-performance, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, and Parasoft, a global leader in automated software testing, jointly announced the establishment of the global partnership to provide the robust software testing solutions for Andes RISC-V automotive platform according to the rigorous ISO 26262 certification process.

Parasoft C/C++test integrates seamlessly with the AndeSight™ integrated development environment. With these combined tools, software developers gain the ability to configure fast and scalable CI/CD (Continuous Integration / Continuous Delivery) pipelines and automate the testing process. Parasoft provides a complete set of testing solutions for the automotive safety life cycle, shorten the stringent certification process for automotive products, and speed up the time to market for customers.

The safety-enhanced AndesCore™ N25F-SE is the first RISC-V CPU IP certified to be fully compliant with ISO 26262 functional safety standards, including Parts 2, 4, 5, 8 and 9, for the development of automotive applications. The N25F-SE is a 32-bit RISC-V CPU core that supports standard IMACFD extensions, including efficient integer instructions and single/double precision floating point instructions. It incorporates the Andes V5 extension instructions to further boost performance and reduce code size. The efficient 5-stage pipeline of the N25F-SE provides a good balance of high operating frequency and compact design. Like its sought-after cousin the N25F, the N25F-SE comes with rich configurable options, all of which are fully certified, and thus SoC design teams are not limited by one fixed CPU configuration when offering automotive solutions.

The joint collaboration ensures ISO 26262 standards by enabling containerized deployments of the AndeSight™ IDE with Parasoft C/C++test and help improve flexibility and productivity for developers. It reaps the benefits of running these pre-packaged containers when performing static analysis and unit testing.

About Parasoft

Parasoft helps organizations continuously deliver quality software with its market-proven, integrated suite of automated software testing tools. Supporting the embedded, enterprise, and IoT markets, Parasoft’s technologies reduce the time, effort, and cost of delivering secure, reliable, and compliant software by integrating everything from deep code analysis and unit testing to web UI and API testing, plus service virtualization and complete code coverage, into the delivery pipeline. Bringing all this together, Parasoft’s award winning reporting and analytics dashboard delivers a centralized view of quality enabling organizations to deliver with confidence and succeed in today’s most strategic ecosystems and development initiatives — cybersecure, safety-critical, agile, DevOps, and continuous testing.

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion since 2021 and continues to rise. In the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion.

For more information, please visit https://www.andestech.com/en/homepage

Follow Andes on Twitter, LinkedIn, YouTube and Facebook. 

Continue ReadingAndes Technology and Parasoft Collaborate to Provide Seamless Software Testing Tools for Automotive Functional Safety Applications

Small Code, High Performance: Latest IAR Embedded Workbench for RISC-V leverages CoDense™ from Andes

IAR Embedded Workbench for RISC-V v3.11 and Andes CoDense™ extension of the AndeStar™ V5 RISC-V processors help embedded developers to shrink their code size and increase their applications’ performance.

Uppsala, Sweden – November 16, 2022 – IAR Systems®, the world leader in software and services for embedded development, has just announced the full support of their latest release of IAR Embedded Workbench for RISC-V for the CoDense™ extension of Andes Technology’s AndeStar™ V5 RISC-V processor. CoDense™ is a patented extension of the processor’s ISA (Instruction Set Architecture) which helps IAR’s toolchain to generate a compact code – for saving flash memory on the target processor while the previously supported AndeStar™ V5 DSP/SIMD and Performance extensions help deliver higher application performance. IAR Systems has already supported the AndesCore™ RISC-V CPU IP at an early stage, offering customers a complete development toolchain including the powerful IAR C/C++ Compiler™ and a comprehensive debugger, which is also available in an ISO 26262 conforming functional safety certified edition.

Andes is a founding Premier member of RISC-V International and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions. The joint solutions from Andes and IAR Systems with their robust design methodology for safety applications help customers accelerating development including the certification process and therefore their products’ time to market. CoDense™ in AndeStar™ V5 is an Andes-extended feature for code size compression on top of the extensible RISC-V standard instructions. The extension has already been proven in more than 10 billion SoCs with AndeStar™ V3 processors. Besides the support for CoDense™, the latest version 3.11 of the IAR Embedded Workbench for RISC-V comes with a “P” extension 0.9.11 support (Standard Extension for Packed-SIMD Instructions) and enhanced SMP (Symmetric Multi-Processing) and AMP (Asymmetric Multi-Processing) multicore debugging. Developers will also appreciate the new IAR Build and IAR C-SPY Debug extensions for Visual Studio Code, so they can utilize IAR Systems’ powerful tools for building and debugging their code within the Visual Studio Code editor.

The proven IAR Embedded Workbench is on the rise among RISC-V developers with its best-in-class code size optimizations, which allows companies to use smaller devices or add even more functionality to an existing platform. The code is generated using the toolchain’s advanced optimization technology and convinces in CoreMark tests from the EEMBC Certification Lab with its fast code and industry-leading performance. The included C-SPY Debugger gives developers full control of the application in real-time, amongst others by using complex breakpoints, profiling, code coverage, timeline with interrupt, and power logging. Fully integrated code analysis tools ensure compliance with specific standards like MISRA C (2004 and 2012) as well as the best programming practices like Common Weakness Enumeration (CWE) and CERT C Secure Coding Standard. Being certified for functional safety development itself, the IAR Embedded Workbench for RISC-V comes with a safety report and safety guide for ten different standards, e.g. for automotive or industrial applications.

“We are glad that IAR Systems provides full support to AndeStar™ V5 RISC-V processors, especially including the enhancement of the patented CoDense™ extension in this release,” said Dr. Charlie Su, President and CTO of Andes Technology. “CoDense™ increases the code density significantly by double digits and is very welcome in MCU or IoT applications. We look forward to the competitive combination of IAR Embedded Workbench with AndeStar™ V5 RISC-V extensions with up to 30 percent higher performance made available to the RISC-V community.”

“Thanks to our close cooperation with Andes, we provided early support for the AndeStar™ V5 DSP/SIMD and Performance extensions and now full support for Andes CoDense™, enabling code size compressions on top of RISC-V C-extension,” said Anders Holmberg, CTO at IAR Systems. “The balance between code size and performance can make a real difference for total return on investment from a product or project. With CoDense™ support, we give our users the power to tip this balance in their favor.”

For more information on the IAR Embedded Workbench for RISC-V, the functional safety-certified edition of the tool suite, and IAR Systems’ overall offering for RISC-V, please visit https://www.iar.com/riscv.

IAR Systems, IAR Embedded Workbench, Embedded Trust, C-Trust, C-SPY, C-RUN, C-STAT, IAR Visual State, I-jet, I-jet Trace, IAR Academy, IAR, and the logotype of IAR Systems are trademarks or registered trademarks owned by IAR Systems AB. All other product names are trademarks of their respective owners.


About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion since 2021 and continues to rise. In the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion.

For more information, please visit https://www.andestech.com/en/homepage

Follow Andes on Twitter, LinkedIn, YouTube and Facebook.

About IAR Systems

IAR Systems provides world-leading software and services that accelerate developer productivity in embedded development and embedded security, enabling companies worldwide to create and secure the products of today and the innovations of tomorrow.

IAR Systems supports 15,000 devices from over 200 semiconductor partners, serving some 100,000 developers working for a mix of Forbes 2000 companies, SMEs, and startups. Founded in 1983, IAR Systems is still headquartered in Uppsala, Sweden, with more than 220 employees in 14 offices distributed across APAC, EMEA, and North America. IAR Systems is owned by I.A.R. Systems Group AB, listed on NASDAQ OMX Stockholm, Mid Cap (ticker symbol: IAR B). Learn more at www.iar.com.


Andes Technology Media Contact:

Jonah McLeod

Phone: +1-510-449-8634

E-mail: Jonahm@andestech.com

IAR Systems Media Contact:

Rafael Taubinger

Phone: +46 18 16 78 00

Email: rafael.taubinger@iar.com

Continue ReadingSmall Code, High Performance: Latest IAR Embedded Workbench for RISC-V leverages CoDense™ from Andes

Andes Technology Unveils the AndesCore™AX60 Series, an Out-of-Order Superscalar Multicore RISC-V Processor Family

The AX65, the First Member of the AX60 Series, Offers Leading Performance Based on Next-generation CPU Micro-architecture

Santa Clara, California — November 2, 2022 — Today, at Linley Fall Processor Conference 2022, Andes Technology, a leading provider of high efficiency, low power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, reveals its top-of-the-line AndesCore™ AX60 series of power and area efficient out-of-order 64-bit processors. The family of processors are intended to run heavy-duty OS and applications with compute intensive requirements such as advanced driver-assistance systems (ADAS), artificial intelligence (AI), augmented/virtual reality (AR/VR), datacenter accelerators, 5G infrastructure, high-speed networking, and enterprise storage.

The first member of the AX60 series, the AX65, supports the latest RISC-V architecture extensions such as the scalar cryptography extension and bit manipulation extension. It is a 4-way superscalar with Out-of-Order (OoO) execution in a 13-stage pipeline. It fetches 4 to 8 instructions per cycle guided by highly accurate TAGE branch predictor with loop prediction to ensure fetch efficiency. It then decodes, renames and dispatches up to 4 instructions into 8 execution units, including 4 integer units, 2 full load/store units, and 2 floating-point units. Besides the load/store units, the AX65’s aggressive memory subsystem also includes split 2-level TLBs with multiple concurrent table walkers and up to 64 outstanding load/store instructions.

AX65 supports multicore cluster with cache coherence to scale out performance. Each core has 64KB private instruction and data caches. The cluster contains up to 8 cores, an in-cluster coherence manager and a shared cache up to 8MB. Its IO coherence interface keeps all AX65 caches coherent with respect to the external IO transactions and allows ease of SoC integration. The coherence manager and the shared cache can use a clock asynchronous to the cores for overall performance optimization in SoC implementations. Moreover, AX65 supports RISC-V standard external debug and instruction trace interfaces to facilitate fast system development, analysis and debugging.

“With hundreds of licensees and billions of chips embedding AndesCore™, Andes has proved it as the CPU IP vendor to rely on. Our mission is to continue to provide a comprehensive lineup of processor IPs to support a wide range of applications from tiny MCUs to datacenter accelerators, offer efficient control processing as well as powerful compute acceleration, and run bare metal, RTOSes and Linux. We are excited to announce our top-of-the-line family of processors, the AX60 series, to further expand our portfolio. ” said Dr. Charlie Su, President and CTO of Andes Technology. “The AX65 is to offer 2x performance in large benchmarks over the previous high-end core, the AX45, at the same frequency. In addition, it is capable of operating at 2.5GHz at 7nm process, 25% over the AX45. With the great boost in performance, the AX65 processor addresses the emerging requirements of a wide range of applications looking to raise control processor performance in the current high-performance SoCs.”

The AndesCore™ AX65 is to be available for lead customers in mid-2023 through the early access program and for general customers by the end of the same year. For further information about the AX65 and the AX60 series processors, please contact Andes Technology.

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes is publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube! 

Press Contact:

Jonah McLeod

+1 (510) 449-8634

Jonahm@andestech.com

Hsiaoling Lin

+886-3-6687253 ext.644

hllin@andestech.com

Continue ReadingAndes Technology Unveils the AndesCore™AX60 Series, an Out-of-Order Superscalar Multicore RISC-V Processor Family

Andes Announces the N25F-SE Processor, the World First RISC-V CPU IP with ISO 26262 Full Compliance

Systematic failures and random hardware failures can be mitigated by development process and safety designs of the safety-enhanced N25F-SE

HSINCHU, TAIWAN – October 17, 2022 – Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, today announces its safety-enhanced AndesCore™ N25F-SE is the first RISC-V CPU IP certified to be fully compliant with ISO 26262 functional safety standards for the development of automotive applications. SGS-TÜV Saar GmbH, an independent functional safety certification body, has assessed and completed product audit process for N25F-SE with achieved functional safety for ASIL B (Automotive Safety Integrity Level B) applications, according to all applicable ISO 26262 series of standards including Parts 2, 4, 5, 8 and 9.

AndesCore™ N25F-SE. The N25F-SE is a 32-bit RISC-V CPU core that supports standard IMACFD extensions, including efficient integer instructions and single/double precision floating point instructions. It incorporates the Andes V5 extension instructions to further boost performance and reduce code size. The efficient 5-stage pipeline of the N25F-SE provides a good balance of high operating frequency and compact design. Its flexible interfaces greatly simplify SoC designs. Like its sought-after cousin the N25F, the N25F-SE comes with rich configurable options, all of which are fully certified, and thus SoC design teams are not limited by one fixed CPU configuration when offering automotive solutions.

ISO 26262 and ASIL-B Applications. ISO 26262 defines functional safety as the “absence of unreasonable risk due to hazards caused by malfunctioning behavior of electrical/electronic systems”. To enforce functional safety with a reasonable cost structure, proper safety measures for desired ASIL levels should be applied, from the least stringent ASIL A to the most stringent ASIL D. Examples of electronic systems where ASIL B is sufficient are dashboard, in-car monitoring, keyless entry, lighting control, tire pressure monitoring, vision ADAS, and window control. Either to incorporate new electronic systems on board, or to upgrade existing ones without ISO 26262 compliance, the N25F-SE is well suited for the wide range of applications requiring ASIL B compliance.

Leader of RISC-V Functional Safety. “Andes is the first RISC-V CPU vendor certified, for the development process of automotive processor cores, to be compliant with ISO 26262 standards up to ASIL D in 2020. With the certified development process in place, we formally started our functional safety roadmap to deliver at least one ISO 26262 compliant core every year to cover all segments of performance and features,” said Dr. Charlie Su, President and CTO of Andes Technology. “Andes has developed a wide range of AndesCore™ processors, from driving cost sensitive MCUs to accelerating datacenter AI/ML computations. We are excited to announce our first safety-enhanced AndesCore® the N25F-SE based on the most popular and mature CPU IP family, the 25-series.”

ISO 26262 Full Compliance. The ASIL B fully compliant N25F-SE was developed under considerations on all applicable requirements of ISO 26262 standards by defining tailored safety activities with solid rationales, from the fundamental specification, analysis, and design to verification and many more. It comes with the Safety Package which includes Safety manual, Safety analysis report (FMEDA and more), and Development Interface Outline. Together, the N25F-SE and its Safety Package offer an effective, efficient, and flexible automotive solution. It greatly reduces the time for SoC design teams to certify their ISO 26262 compliant SoCs. In comparison, an ASIL B “ready” solution is without certifying all required ISO 26262 Parts (2, 4, 5, 8 and 9) and thus provides incomplete support for the SoC’s certification; as a result, SoC design teams must go through all the work the CPU IP vendors are supposed to do. In addition, the N25F-SE helps reduce the cost and power consumption for SoCs requiring only an ASIL B processor IP without forcing them to use a double-sized dual-core lock-step solution with ASIL D. “As the only public RISC-V CPU IP company and a leader in the RISC-V ecosystem, we want to raise the awareness of the importance of ISO 26262 full compliance.” Dr. Su stressed.

  • Cidana. “Consumer experience is shaping expectations for In-Vehicle Infotainment (IVI) systems. It is one of the segments evolving rapidly in the automotive industry. Cidana offers the optimized LC3+ codec and makes it available on Andes ISO 26262 compliance platform. Other mainstream audio codecs can be supported based on the required performance,” said Chinn Chin, the Chief Executive Officer of Cidana. “We are looking forward to collaborating with Andes and bringing the Cidana solutions to automotive SoCs powered by the N25F-SE.”
  • Green Hills Software. “We are pleased to expand our production-ready automotive safety solutions to support the safety-certified AndesCore™ 25-Series RISC-V IP core family from the technology leader, Andes Technology,” said Dan Mender, Vice President, Business Development, Green Hills Software. “This combined hardware-software solution for the AndesCore™ N25F-SE gives SoC providers a valuable head-start in offering integrated and optimized production-proven platforms for next-generation vehicle ECUs that require the highest performance and lowest power, with advanced tools that reduce their customers’ time to market and development costs.”
  • IAR Systems. “RISC-V is being adopted at a remarkable speed in applications from the edge to the cloud and now it is entering the automotive market. IAR Systems support the mature and popular Andes RISC-V 25-series processors since its release a few years back in the IAR Embedded Workbench for RISC-V, Functional Safety edition. We are glad to learn that Andes N25F-SE has been certified for full ISO 26262 compliance,” said Rafael Taubinger, Sr. Product Marketing Manager at IAR Systems. “We are looking forward to extending our collaboration with Andes to support its Safety Enhanced processors starting from the N25F-SE enabling our mutual customers to speed up the path to using RISC-V in automotive safety-critical applications.”
  • Parasoft. “We would sincerely congrats on Andes Technology’s N25F-SE been certified to the ISO 26262 functional safety standard,” said Yue Liu, the President of Parasoft Greater China. “Andes is a leading provider of RISC-V processors, and PARASOFT, a solution provider that helps enterprises deliver defect-free software, is pleased to partner with Andes to further
    deliver RISC-V ecosystem solutions to our customers. I am confident that we will be able to provide a complete suite of testing solutions for the automotive safety lifecycle in the near future, helping customers improve their ability to develop and deliver high quality software.”
  • Virtual Open Systems. “At Virtual Open Systems we are working with Andes to enable hypervisor-less mixed criticality virtualization supporting concurrent execution of a certified real time operating system (OS) with a general purpose OS using our VOSySmonitoRV, a low level firmware developed with ASIL certification in mind,” said Daniel Raho, Virtual Open Systems SAS CEO. “We are excited to extend VOSySmonitoRV with support for Andes Safety Enhanced processors starting from the N25F-SE.”

The AndesCore™ N25F-SE is available for licensing now. Over half of a dozen leading SoC companies are already developing in-vehicle applications with the N25F-SE. Following the N25F-SE, the D25F-SE with DSP/SIMD extension and Bit Manipulation extension is expected to be available in early 2023.

 

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes is publicly-listed
company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit
cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annualvolume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed10 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube!

 

Press Contact:

Jonah McLeod

+1 (510) 449-8634

Jonahm@andestech.com

 

Hsiaoling Lin

+886-3-6687253 ext.644

hllin@andestech.com

Continue ReadingAndes Announces the N25F-SE Processor, the World First RISC-V CPU IP with ISO 26262 Full Compliance

Andes Technology Announces Return of the Annual RISC-V CON on October 18th in the San Jose Airport DoubleTree Hotel

RISC-V CON Features Keynotes from Andes, Intel, Sonical, Crypto Quantique, Green Hills Software and Imperas

SAN JOSE, CA – October 10, 2022—Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, announces the return of its annual RISC-V CON on October 18th in the San Jose Airport DoubleTree Hotel. The RISC-V CON program will include keynotes from Intel Foundry Services, Intel RISC-V Ventures, SoC developer Sonical, and Andes along with technical talks and panel from RISC-V ecosystem partners including Crypto Quantique, Green Hills Software, IAR Systems and Imperas.

Andes Technology President & CTO, Dr. Charlie Su, will begin the program at 10:00 AM with his presentation, “Expanding the RISC-V Horizon.” “It is no secret that RISC-V architecture is growing, its membership is rising, and the RISC-V ecosystem is flourishing,” Dr. Su observed. “All in an unprecedented speed. In my talk, I will examine the expanding range of applications RISC-V serves and how Andes RISC-V solutions help drive this open instruction set architecture’s fast adoptions. I will also talk about Andes RISC-V cores coming on the horizon.”

Keynotes from Bob Brennan, Vice President of Intel Foundry Services and Vijay Krishnan, General Manager, RISC-V Ventures of Intel will respectively address how RISC-V flourishes in a new foundry era and how Intel enables RISC-V for AIoT and edge applications. Sonical will present their next generation of hearable devices using RISC-V. In addition, RISC-V ecosystem talks from Crypto Quantique, Green Hills Software and Imperas will introduce their optimized RISC-V solutions and tools perfect for applications including IoT, functional safety, security and more.

The conference program runs from 10:00 AM to 4:05 PM with lunch and an evening reception included. During the reception, prize drawings will award personal electronics containing Andes RISC-V CPU IP to lucky attendees. Dan Nenni, founder of SemiWiki.com, the open forum for semiconductor professionals, will moderate the “RISC-V Ecosystem Panel: From Edge to Cloud“ that will begin immediately after lunch. The conference is free and it is open to qualified registrants such as design engineers, engineering managers, marketing people and business development personnel. The exhibition accompanying the conference program will showcase MPU development board from Renesas, AI development kit with camera module from Canaan, high-performance industrial-grade microcontrollers from HPMicro, Bluetooth development kit from Telink and Arduino-compatible boards containing RISC-V CPU IP as well as Sonical detailing their Headphone 3.0., the next generation of hearable devices, that unlocks untapped resource of biometric data. To register,  click https://Andes_RISC-V_CON_2022_US.eventbrite.com/?aff=PR

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube! 

 

Continue ReadingAndes Technology Announces Return of the Annual RISC-V CON on October 18th in the San Jose Airport DoubleTree Hotel

Andes Technology Corp. Announces Its RISC-V CPU IP Serves as the Computing Engine in the New Renesas R9A02G020 MCU ASSP

Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced Andes’ entry-level RISC-V core serves as the computing engine in the new G020 RISC-V MCU ASSP from Renesas Electronics Corporation (TSE: 6723), a premier supplier of advanced semiconductor solutions. The CPU IP core, based on AndeStar™ V5 RISC-V architecture, affords easy configurability, low power consumption, high performance and small silicon footprint—all useful functionality in embedded applications. In addition, V5 CoDense™ extension offers additional saving in flash memory.

“The incorporation of the Andes entry-level RISC-V processor IP into the R9A02G020 MCU ASSP adds a significant flexibility for system designers building motor control system solutions,” said Frankwell Lin, CEO of Andes Technology Corp. “This CPU is an ultra-compact, low-power and performance-efficient RISC-V core with rich interfaces for SoC integration. It can deliver industrial leading 3.95 CoreMark/MHz and 1.80 DMIPS/MHz of performance for a wide range of embedded applications. We are excited to provide this small but powerful RISC-V core to Renesas as the computing engine of R9A02G020 MCU ASSP. ”

“As the first RISC-V MCU ASSP product, R9A02G020 is specifically optimized for advanced motor control systems,” said Sailesh Chittipeddi, Executive Vice President, General Manager of Renesas’ IoT and Infrastructure Business Unit. “Alongside ecosystem partners, this provides a complete, production-ready motor control system solution and reduces customer development costs. The R9A02G020 provides the foundation for a turnkey motor control solution including Renesas specialized partners’ software.”

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion since 2021 and continues to rise. In the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion.

For more information, please visit https://www.andestech.com/en/homepage

Follow Andes on Twitter, LinkedIn, YouTube and Facebook.

About Renesas Electronics Corporation

Renesas Electronics Corporation (TSE: 6723) delivers trusted embedded design innovation with complete semiconductor solutions that enable billions of connected, intelligent devices to enhance the way people work and live. A global leader in microcontrollers, analog, power, and SoC products, Renesas provides comprehensive solutions for a broad range of automotive, industrial, infrastructure, and IoT applications that help shape a limitless future. Learn more at renesas.com. Follow us on LinkedIn, Facebook, Twitter, and YouTube.

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All names of products or services mentioned in this press release are trademarks or registered trademarks of their respective owners.

Continue ReadingAndes Technology Corp. Announces Its RISC-V CPU IP Serves as the Computing Engine in the New Renesas R9A02G020 MCU ASSP

Andes Technology Corp. Announces its Contribution to the Intel Pathfinder for RISC-V

AndesCore™ AX45MP 64-bit Multicore Processor and NX27V 64-bit Vector Processor, Both with AXI-based AE350 Platform, Are Available in Intel® FPGA Based Pre-silicon Development Tools.

SAN JOSE, CA – August 30, 2022 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, reveals its contribution to the Intel® Pathfinder for RISC-V* for pre-silicon development initiative today.  Andes announced its highly sought 64-bit superscalar multicore AX45MP processor IP and 64-bit vector processor core NX27V with up to 512-bit vector length, both pre-integrated with AXI-based AE350 platform, have been made available in the Intel® Stratix® 10 GX FPGA Development Kit.

“Those two popular RISC-V CPU cores on Andes IP offerings address the requirements of many high-end applications,” said Frankwell Lin CEO of Andes Technology Corp. “Examples are datacenter AI accelerators, storage for enterprise, 5G networks, and AR/VR. By having those two cores available in the Intel® Stratix® 10 GX FPGA Development Kit, SoC design teams can boot Linux OS or upload their critical compute kernels to the FPGA board to quickly explore the benefits of AX45MP and NX27V before first silicon. We are extremely proud of Andes’ contribution to the Intel Incubation & Disruptive Innovation (IDI) Group’s initiative to streamline development flow to leverage Intel Foundry Services state-of-the-art fabs.”

“With Andes Technology Corp. enabling their IP for Intel Pathfinder, SoC designers can easily run interesting software code before finalizing their RISC-V designs,” said Vijay Krishnan, GM, RISC-V Ventures, Intel Corporation. “Intel is committed to accelerating the adoption of RISC-V through a unified, open and standards-based approach.”

To start your journey with Intel Pathfinder for RISC-V, please visit pathfinder.intel.com

* Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion since 2021 and continues to rise. In the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion.

For more information, please visit  http://www.andestech.com/en/homepage/. Follow Andes on Twitter, LinkedIn, YouTube and Facebook.

Andes Technology Media Contact:

Jonah McLeod

Phone: +1-510-449-8634

E-mail: Jonahm@andestech.com

Continue ReadingAndes Technology Corp. Announces its Contribution to the Intel Pathfinder for RISC-V