RISC-V: Redefining AI's Future in Automotive, Data Center, Communications, and IoT
Date: June 27th, 2023 (Tuesday)
Time: 9:30 AM - 5:00 PM

RISC-V is revolutionizing the future of Artificial Intelligence (AI) in industries such as automotive, data center, communications, and IoT. Its open-source instruction set architecture (ISA) provides higher performance, lower power, and compact silicon footprint, features highly desired by these industry segments. RISC-V has gained rapid widespread adoption due to its compact instruction set and extensibility. The upcoming Andes RISC-V CON, an annual conference organized by Andes Technology, will focus on the theme of "RISC-V: Redefining AI's Future in Automotive, Data Center, Communications, and IoT" The event will provide a perfect opportunity to connect with the RISC-V community and showcase the latest trends, market developments, emerging applications, and technological breakthroughs in this revolutionary ISA.



Welcome Address

Frankwell Lin, Chairman and CEO, Andes Technology

RISC-V On The Road To Ubiquity: Maturing The RISC-V Software Ecosystem

Frankwell Lin

Philipp Tomsich, Chair, RISC-V Software Committee

RISC-V Ecosystem Partner Speech: TSMC

Sanjay Dave, Deputy Director, TSMC

Firing On All Cylinders with Andes RISC-V Processors

Dr. Charlie Su, President & CTO, Andes Technology

RISC-V has been adopted with an amazing speed in diverse applications from general-purpose tiny MCUs, Linux-capable MPUs, 5G networking, enterprise storage to AI/ML accelerators with novel technologies such as compute-in-memory and photonics. For sure, RISC-V is firing on all its cylinders, and Andes and customers are playing a major part of it. In this talk, we will give an overview of Andes RISC-V processor lineup and showcase examples of recently disclosed RISC-V applications powered by AndesCore™. We will then talk about our highend offerings, including the out-of-order processor AX65, the 1024-bit vector processor AX45MPV, and the latest version of popular Andes Custom Extension™ (ACE) for DSA. They will help drive the next wave of RISC-V growth in AI, Automotive, Communication and more.


RISE Project

Barna Ibrahim, Vice Chair, RISE Project

RISC-V SoC Vendor:EdgeQ

Adil Kidwai, VP and Head of Product Management, EdgeQ


RISC-V Ecosystem Panel: Open-Source Is Transforming AI And Hardware

Moderator: Dylan Patel, SemiAnalysis, Chief Analyst


Andrew Feldman, Cerebras

Horace He, Meta

Charlie Cheng, Polyhedron

Raja Khoduri, Stealth Startup

Jim Keller, Tenstorrent

In the rapidly evolving landscape of Artificial Intelligence (AI) and hardware, open-source principles have become a key driver of innovation. This talk will explore the transformative power of open source in AI model development, deployment, and hardware, with a particular focus on the exciting advances being made in the RISC-V ecosystem.

We will begin by discussing the Meta LLAMA model, a prominent open-source AI model that represents a significant leap forward in the field and kicked off a new open-source revolution in large language models. This kicked off an entire wave of open-source models including from firms such as a from Cerebras open-source model.

We will explore how these developments are influencing the broader AI and hardware landscape. The open-source movement is not limited to software alone. It is equally transforming hardware, as exemplified by the RISC-V architecture, an open-source instruction set architecture that is fostering a new level of innovation and collaboration in the hardware community. Through these case studies and more, we will highlight the potential of open-source for democratizing access to advanced technologies, accelerating the pace of innovation, and fostering a collaborative and inclusive global community of AI researchers and practitioners.

Join us as we uncover the future of AI and hardware through the lens of open-source.

Exploring Latest Andes RISC-V Products for Automotive and AIoT

Samuel Chiang, Deputy Director of Marketing, Andes Technology

Recently, RISC-V has been making significant strides in high-growth areas such as automotive, AI, and IoT. We are not only witnessing rapid advancements in RISC-V microprocessor development for these applications but also seeing maturity in other key building blocks, including development tools, libraries, and higher-level software stacks. These advancements provide compelling solutions for designers aiming to develop products for these segments. In this talk, we will update the audience on the progress of Andes' safety-enhanced cores, specifically the 25-SE series, and its third-party solutions targeting the automotive segment. We will also discuss the compact, secure, and versatile D23 core, which targets the IoT segment. Additionally, we will introduce the newly announced AndesAIRE™ I350 deep learning accelerator and NN-SDK designed for edge and endpoint inference.

Virtual platform use in early artificial intelligence software exploration influences SoC architectures

Larry Lapides, VP Worldwide Sales, Imperas Software

This talk outlines the software driven approach for architectural exploration to optimize Andes ACE extensions for your applications using the Imperas reference models and analysis tools. Plus, the key advantage of Fixed-Platform-Kits with the key go-to-market support for end users.


Safe and Secure Software Solutions for Andes RISC-V

Chuck Brokish, Director Of Automotive Business Development, Green Hills Software

Green Hills Software and Andes Technology offer combined capabilities for the AndeStar™ V5 Architecture, enabling the efficient development and confident deployment of RISC-V-based designs in systems with critical requirements for functional safety and security. Green Hills’ software offering features real-time operating systems, powerful compilers and advanced C/C++ development tools that draw upon the company’s 40-years of microprocessor experience.

Professional Tools for Professional Developers

Shawn Prestridge, FAE Manager, IAR US

IAR provides a complete development system for RISC-V development that includes CoreMark benchmark-leading optimizations for size and speed, graphical multi-core and multi-architecture simultaneous debugging, trace debugging, and optional Functional Safety certification. Additionally, our tools support the addition of custom instructions on your RISC-V core to allow you full control of your RISC-V development. In this short session, we will highlight the features that separate a professional toolchain from the rest; after all, you’re a professional developer, and you deserve to use the best tools available!

Q&A / Lucky Draw

Evening reception


Frankwell Lin,
Chairman and CEO, Andes Technology

Dr. Charlie Su,
President & CTO, Andes Technology

Samuel Chiang,
Deputy Director of Marketing, Andes Technology

Philipp Tomsich,
Chair, RISC-V Software Committee

Sanjay Dave,
Deputy Director, TSMC

Barna Ibrahim,
Vice Chair, RISE Project

Adil Kidwai,
VP and Head of Product Management, EdgeQ

Dylan Patel,
Chief Analyst, SemiAnalysis

Horace He,

Andrew Feldman,

Jim Keller,
CEO, Tenstorrent

Raja Khoduri,
Stealth Startup

Charlie Cheng,
Managing Director, Polyhedron LLC.

Larry Lapides,
VP Worldwide Sales, Imperas Software

Chuck Brokish,
Director of Automotive Business Development

Shawn Prestridge,
FAE Manager, IAR US