Hsinchu, Taiwan – Sep. 7, 2023 – Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today proudly announces general availability of the high-performance AndesCore™ AX45MPV multicore vector processor IP. The AX45MPV is the third generation of the award winning AndesCore™ vector processor series. Equipped with powerful RISC-V vector processing and parallel execution capability, it targets the applications with large volumes of data such as ADAS, AI inference and training, AR/VR, multimedia, robotics, and signal processing.
Andes and Meta started collaboration on datacenter AI with RISC-V vector core from early 2019*(See Remarks). Andes later unveiled the AndesCore™ NX27V, marking a significant milestone as the industry’s first commercial RISC-V vector processor core with the capability of generating up to 4 512-bit vector (VLEN) results per cycle, at the end of 2019. It immediately attracted the attention of worldwide SoC design teams working on AI accelerators, and has landed over a dozen datacenter AI projects. Since then, the RISC-V vector processor cores have become the choice for ML and AI chip vendors.
With the goal to further raise the compute density, the AX45MPV extends the capabilities of the dual-issue 8-stage pipeline, Linux support and multicore of the AX45MP with the powerful vector processing unit inherited and enhanced from its predecessor, the NX27V. While the AX45MPV is essentially a Linux application processor with datacenter grade AI capabilities, its support for Linux and multicore can be left out to form an efficient and powerful compute processor in processing elements (PEs) of a large compute array. The dual-issue capability combined with up to 6 1024-bit vector (VLEN) results per cycle in the AX45MPV can provide more than 3X performance comparing with its predecessor. To fully exploit its higher computation power, the AX45MPV offers two 1024-bit memory interfaces. The new high-bandwidth vector local memory (HVM) option provides 1 or 2 HVM bank ports, ideal for vector loads/stores, and an external DMA engine to move chunks of data in the background through an AXI-based HVM Access Port. For computation tasks requiring an integrated coprocessor control along with data transfer, the versatile Andes Streaming Port (ASP) available since the first Andes vector processor is the best solution. By combining the ASP and the HVM ports, the processor effectively doubles its memory bandwidth by, say, being able to load 2 vector data per cycle. The AX45MPV also supports the latest ACE (Andes Custom Extension™), which facilitates customers to create their own RISC-V styled vector instructions. For example, ACE can be used to accelerate nonlinear math functions such as SoftMax on Transformer AI.
“Andes has been serving datacenter AI customers since 2019 with RISC-V Vector architecture and has accumulated rich experience. Equipped with the powerful 1024-bit vector unit, efficient support of multicore and Linux, and versatile configurations, the third generation of Andes vector processors AX45MPV is specially tailored for Large Language Models (LLMs). With the surge of generative AI applications in 2023, we see the AX45MPV taking the center stage in AI and Machine Learning segments beyond the Cloud.”, said Dr. Charlie Su, President and CTO of Andes Technology.
Some customers from Asia and North America have already licensed the AX45MPV, and more are evaluating it. Their applications cover a wide range from the cloud to the edge. The AX45MPV standard product package, without Linux support, is available immediately. Its advanced product package will come with Linux support and will be available in Q4 2023.
About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! !
*Remarks: MTIA: First Generation Silicon Targeting Meta’s Recommendation Systems, ISCA ’23: Proceedings of the 50th Annual International Symposium on Computer Architecture, June 2023
