20191114_2019 RISC-V CON Beijing

RISC-V, an open instruction set architecture (ISA), has rapidly evolved into a new mainstream embedded processor technology. Andes positions itself as a professional and reliable vendor of RISC-V processors and solutions and launched several new RISC-V based products recently. Andes RISC-V Con will focus on this disruptive technology, demonstrating its benefits and identifying commercial strategies.

Come listen to speeches and many informative topics to help you quickly bring designs based on the open RISC-V ISA to market.

2019 RISC-V CON Beijing
Date: 14 Nov , 2019
Place: Beijing, China  
Event website  

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20191015_2019 RISC-V CON Silicon Valley

2019 Andes RISC-V CON Silicon Valley
Date: 15 Oct, 2019
Venue:  David’s Restaurant
→Download presentation slides from the event website

RISC-V, an open instruction set architecture (ISA), has rapidly evolved into a new mainstream embedded processor technology. Andes positions itself as a professional and reliable vendor of RISC-V processors and solutions and launched several new RISC-V based products recently. Andes RISC-V Con will focus on this disruptive technology, demonstrating its benefits and identifying commercial strategies.

Come listen to speeches and many informative topics to help you quickly bring designs based on the open RISC-V ISA to market.

Continue Reading20191015_2019 RISC-V CON Silicon Valley

Andes Technology Launches RISC-V FreeStart Program with its Commercial-Grade CPU N22

AndesCore™ RISC-V CPU IP N22 integrated with interrupt controller, local memory, instruction cache, debug support, and an optional AHB platform

 

HSINCHU, TAIWAN – June 10, 2019 – Andes Technology Corporation, a leading supplier of high performance, low-power, compact 32/64-bit CPU cores embedded in over 1 billion SoC in 2018 alone, today announces its RISC-V FreeStart program. The program offers an easy and fast way to build a solid SoC foundation on the commercial-grade RISC-V CPU core N22, available for free download. AndesCore™ N22 is an entry-level, ultra-compact, low-power and performance-efficient RISC-V CPU IP. It delivers the highest 3.95 Coremark/MHz in its class, and offers rich configurable features, including multiplier, interrupt controller, local memory, instruction cache, debug support, and an optional AHB platform. With the RISC-V FreeStart program, SoC engineers can begin designing a RISC-V based SoC without budgeting CPU IP upfront.

“RISC-V is finding rapid adoption and creating high demand, especially in MCU level applications,” said Andes Technology President, Frankwell Jyh-Ming Lin. “Designers are seeking a small, efficient, and yet high performance-efficient commercial RISC-V core to construct their creative SoCs. Unlike open source RISC-V CPUs which are with limited features and lack of documents, and need to be verified by SoC designers first, users of the commercial-grade N22 can skip this time-consuming task which adds nothing to the value of their final SoC and instead spend their precious design resources on their true value added.”

“The N22 CPU is a small, 2-stage pipeline 32-bit RV32I/EMAC RISC-V CPU core, 16 or 32 general purpose registers, multiplier, atomic and compressed instructions. It also supports several unique and configurable features such as StackSafe™ for hardware stack protection, PowerBrake for efficient power management, CoDense™ for code size reduction on top of RISC-V C extension, and local memory and instruction cache for performance boost,” stated Andes CTO and Executive Vice President, Dr. Charlie Hong-Men Su. “The program also provides designers the option of 1-year support and a pre-integrated AHB platform with commonly used peripheral IPs, thus saving the time of sourcing and integrating these into their design. In addition, the RISC-V FreeStart can leverage the AndeSight™ IDE, a professional software development environment with over 15,000 worldwide installations, which has been available for free download.”

Availability

The RISC-V FreeStart program has been launched now. Anyone from industrial professionals to school students is invited to view and sign the online license agreement and download the N22 processor for evaluation purpose. The FreeStart also provides mass production program that allows industry, research institutes and academia to make commercial chips with running royalty or for research purpose but allow path of migration to mass production. Design teams can choose the optional technical support program available through Andes online e-service, which comes with an AHB platform RTL code for SoC integration. Please visit FreeStart.andestech.com or simply fs.andestech.com for more detail.

About Andes Technology

Andes Technology Corporation is a public listed company with well-established technology and teams to develop innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications.

The company delivers the best super low power CPU cores, including the new RISC-V series with integrated development environment and associated software and hardware solutions for efficient SoC design. Up to the end of 2018, the cumulative volume of Andes-Embedded™ SoCs has reached 3.5 billion with 2018 alone contributing over 1 billion.

To meet the demanding requirements of today’s electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers’ needs for quality products and faster time-to-market. Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, and A25MP/AX25MP. 

For more information about Andes Technology, please visit

http://www.andestech.com

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20190912_IP SoC Day Shanghai 2019

When : September 12, 2019

Where : Evergreen Laurel Hotel Shanghai
No. 1136, Zu Chongzhi Road, Pudong New District
Pudong, 201203 Shanghai, China

IP SoC China is the unique one day working conference in China fully dedicated to IP ( Silicon Intellectual property) and IP based Electronic systems.

The event is the annual meeting for IP providers and IP consumers to share information about technology trends, innovative IP Soc designs, IP Soc Market evolution.

Meet the gurus in the field, get expertise about the most advanced IP offer and make the best business decision.  

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