20190423_TSMC Technology Symposium in Santa Clara
Date: 2019/04/23
Place: Santa Clara, CA
Place: Santa Clara, CA
Andes Records a Rapid Growth of Design Wins in 2018 for Its New Family of RISC-V Processor Cores
Andes Signed 21 RISC-V IP Core Licenses in 2018
Throughout the U.S. and Asia across a Wide Range of Applications
HSINCHU, TAIWAN – April 17, 2019 – Andes Technology Corporation, a leading supplier of small, low-power, high performance 32/64-bit embedded CPU cores, including a broad family of RISC-V cores, announced it achieved a record number of design wins for its new family of RISC-V processors during 2018. These include the 32-bit N25F/A25 and 64-bit NX25F/AX25. This represents a dramatic growth in the number of licenses signed soon after introduction of the RISC-V cores. Adoption of the RISC-V architecture is rapidly accelerating in China, spreading throughout the Asia Pacific region, and sweeping the U.S. Over a third of the 21 licensee agreements were signed in China and another third in Taiwan with the rest in the U.S., Korea and Japan. The wins are going into a wide range of application. Nearly half of the sockets are in artificial intelligence designs, where RISC-V plays an important role. Other applications adopting RISC-V include block chain, communications, fingerprint recognition, FPGA, IoT, security applications, and solid state storage devices.
The rapid growth of RISC-V proves that increasing numbers of developers are adopting RISC-V architecture for their applications. Key to Andes successful lead in the RISC-V market was its rapid adoption of the RISC-V architecture. “We are thrilled at the customer acceptance of our RISC-V product line,” declared Andes Technology President, Frankwell Jyh-Ming Lin. “We joined the RISC-V Foundation as founding member because we were convinced of the commercial viability of the RISC-V CPU. In addition, the RISC-V architecture contains many of the fundamental elements already in our existing CPU IP product family. As a result, once the RISC-V foundation published the instruction set architecture (ISA), Andes was able to quickly develop our line of 32/64-bit RISC-V IP cores.” Owning to Andes’ rich experience in providing CPU IP, Andes achieved competitive advantage by meeting customers’ needs for RISC-V processor cores. “The advantage our IP has over competitive offerings is its ability to use special extensions already in existing Andes’ CPU IP to improve performance, plus other features such as PowerBrake, to reduce peak CPU power consumption; StackSafe™, to enhance system safety; and CoDense™ to reduce overall code size for a design.”
Andes RISC-V cores are based on AndesStar™ V5 architecture with single and double precision floating point support for high-precision data computations and MMU (Memory Management Unit) for Linux applications. In addition to the compactness, modularity and extensibility advantages of RISC-V ISA, Andes also provides customer-instruction extension capability to facilitate the design of Domain-Specific Architecture/Acceleration (DSA). “Andes’ RISC-V solution provides the capability to add custom extensions using our powerful Andes Custom Extension™ (ACE) tool,” stated Andes CTO and Executive Vice President, Dr. Charlie Hong-Men Su. “With ACE customers can add extensions specifically for their target applications to eliminate software bottlenecks and significantly improve runtime performance. While other CPU cores do not allow designers to add their own instructions to a CPU architecture, Andes provides COPILOT (Custom-OPtimized Instruction deveLOpment Tool) for ACE, which does the tedious but essential work needed to add a new instruction to a CPU ISA: creates the instruction’s RTL, its instruction set simulator, and its tool extensions—compiler, assembler, and debugger—automatically.”
As the recent popularity of RISC-V is rising among the CPU IP industry especially in China, the growth of RISC-V adoption and ecosystem is expected to rapidly accelerate.
20190410-20190411_Linley Spring Processor Conference
Frankwell Lin, President of Andes Technology, will present at Linley Spring Processor Conference 2019. The topic will be “A New RISC-V Core IP for Low Power Yet High Performance” at 10:20 on 4/10. He will provide an update of the technology porting status, advantages, and upcoming product plans of Andes. Date: April 10-11, 2019 Venue: Hyatt Regency, Santa Clara, US.
Event website
20190401-20190404_RISC-V Tour (North America)
Date: 2019/4/1
Venue: The Conference Center at Waltham, Boston
Date: 2019/4/2
Venue: Commons Conference, Austin
Date: 2019/4/3
Venue: AV Irvine, Irvine
Date: 2019/4/4
Venue: WDC Milpitas, San Jose
20190521_RISC-V Con Shenzhen
2019 Andes RISC-V Con Shanghai
RISC-V, an open instruction set architecture (ISA), has rapidly evolved into a new mainstream embedded processor technology. Andes positions itself as a professional and reliable vendor of RISC-V processors and solutions and launched several new RISC-V based products recently. Andes RISC-V Con will focus on this disruptive technology, demonstrating its benefits and identifying commercial strategies.
Come listen to speeches and many informative topics to help you quickly bring designs based on the open RISC-V ISA to market.
Date: March 21st (Thu.)
Time: 13:30~17:30
Venue: Grand Mercure Oriental Ginza Shenzhen
Event Website
Click to Register
20190519_RISC-V Con Shanghai
2019 Andes RISC-V Con Shanghai
RISC-V, an open instruction set architecture (ISA), has rapidly evolved into a new mainstream embedded processor technology. Andes positions itself as a professional and reliable vendor of RISC-V processors and solutions and launched several new RISC-V based products recently. Andes RISC-V Con will focus on this disruptive technology, demonstrating its benefits and identifying commercial strategies.
Come listen to speeches and many informative topics to help you quickly bring designs based on the open RISC-V ISA to market.
Date: March 19th (Tue.)
Time: 9:30~17:30
Venue: Shanghai Grand Trustel Purple Mountain Hotel
Event website
Click to Register
Andes Technology Announces RISC-V Single-core and Multicore Processors with DSP Instruction Set
Hsinchu, Taiwan. – March 12, 2019 – At the RISC-V Workshop Taiwan cohosted by Andes Technology today, Andes proudly announces the debut of its 32-bit A25MP and 64-bit AX25MP RISC-V multicore processors. The A25MP and AX25MP are the first commercial RISC-V cores with comprehensive DSP instruction extension. With the addition of cache-coherent multiprocessors and the DSP ISA based on the RISC-V P-extension draft Andes donated to the RISC-V Foundation, Andes brings powerful solutions to address the new market and further enriches its RISC-V lineup.
Multiple processor cores working in parallel empower applications such as artificial intelligence and Advanced Driver-Assistance Systems (ADAS) to boost performance of their computation intensive tasks significantly. Furthermore, hardware managed cache coherence simplifies software design considerably for systems with multiple CPUs. The A25MP and AX25MP support up to four CPU cores. They provide efficient cache coherence among private level-1 caches; include an optional shared level-2 cache; and support I/O coherence for bus masters without caches. Operating at over 1GHz in 28nm process with Linux symmetric multiprocessing (SMP) support, the A25MP and AX25MP raise the RISC-V processors to the next performance level and a wider market.
Many embedded applications processing digital signals such as voice, audio and image require efficient DSP instruction set as general-purpose baseline instructions are often not sufficient. As a founding member of the RISC-V Foundation, Andes responded to the popular inquiries for DSP capabilities in the RISC-V ISA by chairing the P-extension Task Group of the RISC-V Foundation, and donating its industry proven DSP/SIMD ISA to kick start the standardization effort. Andes’ new A25MP and AX25MP cores support the P-extension draft. Accompanying the DSP-capable processors are complete supporting tools including compiler, DSP libraries and simulator. Together they enable an over 7 times acceleration in the PNET for MtCNN (Multi-task Cascaded Convolutional Networks) face detection and alignment algorithm. They also provide an order of magnitude performance boost on CIFAR10 image classification benchmark for machine learning, which is a collection of images commonly used to train machine learning and computer vision algorithms.
“For over a decade Andes remains a major CPU IP vendor, and a leading supplier of RISC-V cores including the new N22-series and N25-series cores that serve the ever increasing demand for ultra-compact and high-performance RISC-V processors,” Andes President Frankwell Jyh-Ming Lin said. “Over 150 companies have licensed AndesCore™ processor IP and billions of electronic devices containing Andes CPU IP in a wide variety of applications have shipped globally.”
“The introduction of A25MP and AX25MP RISC-V multicore is a significant advancement for both Andes and the RISC-V community,” said Dr. Charlie Su, CTO and EVP of Andes Technology, “Built upon Andes’ successful processor solutions and solid development support, these powerful multiprocessor IPs with sophisticated DSP instructions as well as floating-point instructions mark the RISC-V architecture’s major step forward in the processor industry. It is truly exciting that Andes RISC-V solutions are being rapidly adopted by the industry since their introduction. We encourage the world to benefit from the developments pioneered by the RISC-V Foundation including Andes Technology.”
Along with the introduction of A25MP and AX25MP, their single-core versions, the previously released 32-bit A25 and 64-bit AX25 with Linux and floating-point support, are now upgraded with the DSP ISA. Also made available is the 32-bit D25F processor, which is an A25 without MMU and S-mode support to closely address DSP applications which do not need to run Linux. All these processor IP’s enjoys the same efficient baseline pipeline of the 25-series processors and the powerful ACE tools for custom instruction design.
For more information about the A25MP/AX25MP multicores, the upgraded A25/AX25, the D25F, and the latest developments of RISC-V P-extension DSP/SIMD ISA, please contact Andes Technology at http://www.andestech.com/.
