2019 Andes RISC-V Con Shanghai
RISC-V, an open instruction set architecture (ISA), has rapidly evolved into a new mainstream embedded processor technology. Andes positions itself as a professional and reliable vendor of RISC-V processors and solutions and launched several new RISC-V based products recently. Andes RISC-V Con will focus on this disruptive technology, demonstrating its benefits and identifying commercial strategies.
Come listen to speeches and many informative topics to help you quickly bring designs based on the open RISC-V ISA to market.
Date: March 21st (Thu.)
Time: 13:30~17:30
Venue: Grand Mercure Oriental Ginza Shenzhen
Event Website
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