RISC-V CON
Silicon Valley

OCT 15, 2019

About RISC-V CON

RISC-V, an open instruction set architecture (ISA), has gained momentum and rapidly evolved into a new mainstream embedded processor technology with a rich ecosystem and a fast-growing number of real-world implementations.

In order to foster stronger collaboration on RISC-V across the computing industry, RISC-V CON will focus on this disruptive technology, demonstrating its benefits and identifying commercial strategies.

With more than 14 years focusing on the CPU IPs, Andes is the most experienced vendor of RISC-V processors and solutions. It has launched several new RISC-V based products recently.

By bringing together industry experts, the goal is to make it easier for other industry players to quickly bring innovative designs based on the open RISC-V ISA to market.

  • There will also be a lucky draw at the end of RISC-V CON where you can win some of the newest and hottest gadgets.
  • Andes Technology reserves the right to verify all registrations.
  • Andes Technology reserves the right to make changes to the program without prior notice.

WHEN

Date: October 15, 2019 (Tue.)
Time: 9:45-14:50

Agenda

Registration

Frankwell Lin

Welcome Remarks

Frankwell Lin, President
Andes Technology

Semico Research

RISC-V Market Update

Jim Feldhan, President
Semico Research

Charlie Su

Powering RISC-V SoCs with 1 to 1,000s AndesCores

Charlie Su, CTO & EVP
Andes Technology

Tea Break

Amazon

AI Compiler for RISC-V

Vin Sharma, Head of Engineering
Amazon SageMaker Neo, AWS AI

Imperas

Software Driven Hardware Design & Verification of Andes RISC-V Processors and SoCs

Larry Lapides, Vice President Sales, Imperas

Lunch

Monte El-Khatib

Faraday RISC-V based ASIC Solution for Edge AI and IoT SoCs

Kyle Weng, VP of Field Application and Marketing, Faraday

Imperas

Panel: Applications Driving RISC-V Adoptions

Moderator: Jim Feldhan
Panelists: Andes, Amazon, Imperas, Faraday

Q&A / Lucky draw

Farewell

Speakers


Frankwell Lin
Andes Technology
President
Frankwell Lin
Andes Technology
President

President Lin started his career being as an application engineer in United Microelectronics Corporation (UMC) while UMC was an IDM with its own chip products, he experienced engineering, product planning, sales, and marketing jobs with various product lines in UMC. In 1995, after four years working on CPU chip product line as business director, he was transferred to UMC-Europe branch office to be its GM when UMC reshaped to do wafer foundry service, he led UMC- Europe to migrate itself from selling IDM products to selling wafer foundry service.

In 1998, after 14 years working in UMC, President Lin switched job to work in Faraday Technology Corporation (Faraday), he lead ASIC business development as starting, then on-and-off leading ASIC implementation, chip backend service, IP business development, industry relationship development (IR), as well as Faraday's spokesperson, in 2004, he started to lead the CPU project spin-off operation of Faraday.

President Lin became co-founder of Andes Technology Corporation (Andes) in 2005 when it was founded; he formally took the position of Andes' President in 2006.

President Lin received BSEE degree of Electrophysics from the National Chiao-Tung University, Taiwan, and MSEE degree of Electrical and Computer Engineering from Portland State University, Oregon, USA. Under his management, Andes has been recognized as one of leading suppliers of embedded CPU IP in semiconductor industry. Andes also won the reputation of a leading technology company with awards such like 2012 EE Times worldwide Silicon 60 Hot Startups to Watch, 2015 the Deloitte Technology Fast 500 Asia Pacific award, etc.

In 2015, President Lin received accolades when awarded the Outstanding Technology Management Performance, Taiwan, for his contribution to the high-tech industry.


Charlie Su
Andes Technology
CTO & EVP
Charlie Su
Andes Technology
CTO & EVP

As a cofounder of Andes, Charlie is in charge of product development and technical marketing. He spent over 12 years in the Valley with technical and management positions at Sun, Afara, C-Cube, SGI/MIPS, and Intergraph. He made key contributions to successful processors such as the Sun multi-core multi-threading UltraSPARC T1/T2 processors, the C-Cube high-performance E-series MPEG codec, the MIPS out-of-order R10K processor, and the Intergraph Clipper VLIW processor. Prior to starting Andes in 2005, he led the CPU/DSP development in Faraday Technology as Chief Architect for 2 years. Charlie got his Ph.D. in CS from UIUC, MSCS from NTHU, and BSEE from NTU.


Kyle Weng
Faraday
VP of Field Application and Marketing
Kyle Weng
Faraday
VP of Field Application and Marketing

Kyle has over 20 years of experience in the semiconductor industry, focused on ASIC design enablement, technical program management, and customer-facing marketing. He serves as field application and marketing vice president at Faraday Technology USA, with strong foresightedness perspective resulting from a solid field engineering and sales foundation.

Before joining Faraday, Kyle worked as a General Manager at Brite Semiconductor USA and has held various technical and marketing roles during his career. Kyle earned his Master of Science in Electrical Engineering degree from New Mexico State University.


Jim Feldhan
Semico Research
President
Jim Feldhan
Semico Research
President

Jim Feldhan founded Semico Research in 1994. A 20-year veteran of the semiconductor industry, he brings his management, forecasting and modeling expertise to Semico, along with a reputation of quality research. Jim designed and developed the research methodologies and report structures, which are the basis for Semico’s Custom Research and Portfolio Services.

Jim also develops Semico’s overall economic outlook as well as performing various semiconductor consulting and forecasting. With a focus on quality, Semico Research has grown to the largest semiconductor-focused consulting and research firm. Jim was formerly the Executive Vice-President and General Manager at In-Stat. As a member of the start-up team there, Feldhan was responsible for the design, methodologies, and implementation of research that was the basis for the Semiconductor Services.

Mr. Feldhan also held various management, marketing and manufacturing positions at GTE Microcircuits and Greyhound/Dial Corporation. Jim received a BS in Business with a minor in Chemistry from the University of Arizona and a MS in Marketing focusing on quantitative statistics and market research from the University of Arizona.


Vin Sharma
Amazon SageMaker Neo, AWS AI
Head of Engineering
Vin Sharma
Amazon SageMaker Neo, AWS AI
Head of Engineering

Vin Sharma leads the Amazon SageMaker Neo team, which provides a cloud service and runtime for machine learning inference based on Treelite, Apache TVM, and other compilers. Before joining Amazon, Vin was a senior director at Intel, leading the development of BMW’s data center infrastructure for autonomous driving R&D. He was responsible for Intel’s big data analytics solutions based on Spark, Hadoop, OpenStack, and KVM in the Data Center Group at Intel for 6 years. Previously, he held various engineering and management roles at HP for 15 years, helping build enterprise security software products based on Linux, Java, XML, and other open source systems software.


Larry Lapides
Imperas
Vice President Sales
Larry Lapides
Imperas
Vice President Sales

Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University's Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley.

exhibitors

  • Andes Technology Corporation is a public listed company with well- established technology and teams to develop innovative high- performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications.

    The company delivers the best super low power CPU cores, including the new RISC-V series with integrated development environment and associated software and hardware solutions for efficient SoC design. Up to the end of 2018, the cumulative volume of Andes-Embedded™ SoCs has reached 3.5 billion with 2018 alone contributing over 1 billion.

    To meet the demanding requirements of today's electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers' needs for quality products and faster time-to-market. Andes Technology's comprehensive CPU includes entry- level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, and A25MP/AX25MP.

    For more information about Andes Technology, please visit
    www.andestech.com

  • Amazon Web Services (AWS) is the world’s most comprehensive and broadly adopted cloud platform, offering over 165 fully featured services from data centers globally. Millions of customers —including the fastest-growing startups, largest enterprises, and leading government agencies—trust AWS to power their infrastructure, become more agile, and lower costs. AWS provides services for broad range of applications including compute, storage, databases, networking, analytics, machine learning and artificial intelligence (AI), Internet of Things (IoT), security, and application development, deployment, and management.

  • Imperas develops and markets state-of-the-art virtual platforms and tools to enable the most comprehensive embedded software development, debug and test solutions available today. The Imperas team has combined advanced simulation algorithms, modeling excellence, and a broad range of tools to produce a system that offers: Fastest Execution Performance, Extensive Library of Accurate Models, and Advanced Development Tools. The Virtual Platform library includes over 200 processor models plus peripheral models and many reference example platforms.

    Andes Certifies the Imperas Models and Simulator as a Reference for Andes RISC-V Cores, the full library of support processor models includes Andes A25, A25MP, AX25, AX25MP, D25F, N25F, NX25F, and N22.

    Additional information is available at:
    www.imperas.com and www.ovpworld.org

  • Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. From specification level to GDSII-in, its flexible business engagement model allows customers to check-in at various design phases in maximizing ASIC implementation efficiency.

    Faraday's comprehensive IP portfolio and best-in-class IP customization service have enabled customers' products to address various applications and market segments effortlessly.

    Since 1993, Faraday has been cooperating with top-tier suppliers of IP, EDA, manufacturing, packaging, and testing, completing more than 2,200 tapeouts resulting in hundreds of millions chips shipped worldwide a year.

  • Lauterbach, the leading manufacturer of microprocessor development tools continues to expand and enhance debug support with theTRACE32 Debugger for RISC-V. Lauterbach’s TRACE32® debug tools have become a favorite with many embedded engineers, and the company is recognized for both engineering excellence and exceptional technical support. TRACE32® supports all the major families of microprocessor cores, covering products from more than 75 silicon companies. The quality and capability of Lauterbach tools enable engineering teams to develop robust code whilst minimizing development time lost to debugging. For RISC-V, Lauterbach TRACE32 provides multicore debugging on individual hardware threads of RISC-V cores, enabling debugging right from the reset vector, which analyses startup codes and other key functions. Lauterbach also provides high-level and assembler debugging for a variety of standard ISA extensions, such as compressed instructions and floating point. It also fully supports the JTAG Debug Transport Module (DTM) in all RISC-V chips. Future development includes support for other debug interfaces such as USB and adding RISC-V trace to our off-chip trace offering.

  • M31 Technology Corporation (6643-TW) is a professional silicon intellectual property (IP) provider. The company was founded in October, 2011 with its headquarters in Hsinchu, Taiwan. M31’s strength is in R&D and customer service. With substantial experiences in IP development, IC design and electronic design automation fields, M31 focuses on providing high-speed interface IP, memory compilers, standard cell library and ESD/IO library solutions. M31’s vision is to be the most trustworthy IP company in the semiconductor industry. For more information please visit www.m31tech.com

Venue

Event venue location info

RISC-V CON
SILICON VALLEY

October 15, 2019 (Tue.) 9:45-14:50

VENUE
David’s Restaurant
5151 Stars and Stripes Drive, Santa Clara, CA

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