20191015_2019 RISC-V CON Silicon Valley


2019 Andes RISC-V CON Silicon Valley
Date: 15 Oct, 2019

Venue:  David’s Restaurant
→Download presentation slides from the event website

RISC-V, an open instruction set architecture (ISA), has rapidly evolved into a new mainstream embedded processor technology. Andes positions itself as a professional and reliable vendor of RISC-V processors and solutions and launched several new RISC-V based products recently. Andes RISC-V Con will focus on this disruptive technology, demonstrating its benefits and identifying commercial strategies.

Come listen to speeches and many informative topics to help you quickly bring designs based on the open RISC-V ISA to market.