Sheila, Author at Andes Technology

Andes Presents Ground-Breaking 27-Series Processor at RISC-V Summit 2019

Post author:Sheila
Post published:2019-12-04
Post category:Press Release

Configurable Vector Processor Enables Scalable Performance Beyond Any IP Core to Date Supported by High-Performance Memory Subsystems

Hsinchu, Taiwan and San Jose, California, December 4^th, 2019 – Andes announces AndesCore™ 27-series CPU cores today and will present it at the RISC-V Summit. The 27-series is the first licensable RISC-V core to deliver to a production licensee the RISC-V Vector instruction extension (RVV), and to sustain the memory bandwidth and efficiency Andes has also re-architected its memory subsystem. Initial delivery of the CPU core has completed to Andes earliest licensee, with production release slated for Q1, 2020. Dr. Charlie Su, Andes Technology CTO and EVP will unveil details of this ground-breaking product at the Summit.

The advent of AI, AR/VR, computer vision, cryptography, and multimedia processing all require complex computation of large volume of matrix data. Unlike other vendor’s advanced SIMD, which has a narrow range of performance dictated by their architecture control, the RVV specification envisions a powerful instruction set with scalable data sizes, flexible microarchitecture implementations, and leaves memory subsystem decisions open for system level optimization. With the 27-series CPU cores, Andes delivers this unprecedented performance and flexibility to the RISC-V community and for the first time, enables RISC-V cores to fill the void in applications even other vendors have not been able to reach.

“The 27-series marks yet another important milestone in both Andes and RISC-V journey, and I couldn’t be more proud of our R&D team for this achievement,” said Andes President, Frankwell Lin. “The RVV extension boldly takes RISC-V beyond any licensable processor core technology into the hottest markets today, and our licensee’s confidence in the R&D team enables Andes to be the first to deliver on this ambitious vision. The team has worked together from specification to delivery in less than nine months. It’s one of the most thrilling journey in Andes history.”

Initially available in the 27-series will be the 32-bit A27, and 64-bit AX27 and NX27V. They benefit from Andes proven 25-series cores, supporting the latest RISC-V specifications, subsystem level components, as well as ecosystem enablement from Andes’ 14-years of R&D development. The A27 and AX27, tailored for applications running Linux, offer 50% higher memory bandwidth than its 25-series predecessors. The NX27V contains a Vector Processing Unit (VPU) which supports the RVV scalable vector instruction set, designed from the ground up to be a Cray-like full vectorization computation unit than the incremental growth from SIMD instructions which some advanced SIMD has evolved from. As such, there is a full Vector Register File (VRF) of user-configurable number of elements per register. Each vector can be arbitrary length, from as small as 64-bit to as large as 512-bit (VLEN) and all the way to 4096-bit by combining up to eight vector registers (LMUL). It also allows each computation of integer, fixed point, floating point, and other AI-optimized representations to be any bit-width from 4 bits to 32 bits, and handles non-divisible last matrix elements in the same loop. The 27-series VPU implements all of these capabilities, and has multiple functional units which are chainable, each can operate in independent pipelines to sustain the computational throughputs needed in critical kernel functions. Fully configured, the VPU can achieve over 30x speedup measured by the key functions in MobileNets, a popular convolution neural networks (CNN). Compared to the popular 128-bit scalar SIMD solution, the NX27V VPU offers 4 times more raw processing power per cycle with additional advantage due to the higher efficiency of vector instruction issuing.

“It’s exciting to see fourteen years of R&D investment all come together in one ambitious project,” said Dr. Charlie Su. “From the vector microarchitecture to the memory subsystem, and all the ecosystems required to enable our licensees, at whatever scale and scope the licensee deems appropriate, Andes has taken RISC-V users to the frontiers of these embedded applications.”

Indeed, the 27-series has vastly expanded its memory subsystem to keep up with the bandwidth required to sustain the computational rate of the VPU, all of which will benefit all customers in general, whether they use the VPU or not. The 27-series now supports multiple outstanding memory accesses inflight so the scalar and vector processors both don’t have to wait for the data during cache misses. In addition, cache pre-fetches allow the memory to prepare data in advance of processor’s needs, thus hiding potential cache misses. Finally, Andes Custom Extension (ACE) interface has been expanded to provide instruction customization to speed up control path as well as to widen data path into the core.

Pricing and Availability:

The 27-series processor beta release has been delivered to Andes’ first licensee in early December, 2019, with production database release in Q1, 2020. Please contact Andes Sales at sales@andestech.com for configuration and pricing of the 27-series processors.

About Andes Technology

Fourteen years after starting from scratch, Andes Technology Corporation is now a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment that serves the rapidly growing global market for embedded system applications. A founding Platinum member of RISC-V Foundation, Andes is the first mainstream CPU vendor that has adopted the RISC-V as the base of its fifth-generation architecture, the AndeStar™ V5. To meet the demanding requirements of today’s electronic devices, Andes delivers highly configurable and performance-efficient CPU cores with full-featured integrated development environment and comprehensive software/hardware solutions to help customers innovate their SoC in a shorter time to market. Since 2018, the yearly volume of SoCs Embedded with Andes CPUs has surpassed the 1-billion mark. Andes Technology’s comprehensive RISC-V CPU families range from the entry-level 32-bit N22, mid-range 32-bit N25F/D25F/A25 and 64-bit NX25F/AX25F, to the high-end multicore A(X)25MP.

RISC-V Foundation Founding Member Andes Technology Turns Platinum

Post author:Sheila
Post published:2019-12-03
Post category:Press Release

Leading RISC-V CPU IP provider deepens commitment to support the development of embedded computing and customized CPU

Hsinchu, Taiwan – December 03, 2019 – Andes Technology Corporation (TWSE: 6533), a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 1-billion diversified SoCs yearly, today announced that it has upgraded its membership in the RISC-V Foundation to Platinum.

Andes Technology joined the RISC-V Foundation in 2016 as a founding member and brought its extensive experience in developing embedded CPU and supporting diversified applications to take RISC-V ISA to the next level. With more than 300 commercial licenses and cumulative shipments exceeding 4 billion SoCs, Andes is the first public CPU IP vendor with the market and technology expertise driving the open-source RISC-V instruction set architecture. Andes’ commitment to the RISC-V community is rooted on its strong belief on open source. It is a major contributor and maintainer of RISC-V open source software such as GNU, LLVM, uBoot, and Linux. Moreover, as the chair of the P-extension (Packed SIMD/DSP) Task Group and co-chair of Fast Interrupt Task Group, Andes continues its key role contributing architecture extensions to the RISC-V Foundation. In addition, Andes also regularly attends the global Technical Committee meetings to closely watch and contribute to other Task Groups.

Andes also participates in the RISC-V Foundation Marketing Committee and APAC Promotion Task Group to help drive RISC-V’s global expansion. The company has joined most every RISC-V workshop in Asia, EU, and the US, and one-day RISC-V roadshows in 15 cities around the world. It participates in important industry events, such as Embedded World, DAC, RISC-V Meetups and many more. In 2019, Andes has given more than 100 public presentations relating to RISC-V promotion. To further promote RISC-V, Andes produces the successful RISC-V CON series across Asia and Silicon Valley aiming to share market trends and leading technology development with RISC-V enthusiasts around the world.

“Andes’ unwavering commitment to RISC-V has continued to inspire and engage the broader ecosystem. The RISC-V Foundation is honored to work with Andes in accelerating momentum and adoption of RISC-V around the world,” said Calista Redmond, CEO of the RISC-V Foundation.

“’The Global AI in IoT market is expected to reach $21.1 billion by 2026 growing at a CAGR of 27.1 percent during the forecast period,’” according to Esticast Research. Choosing a professional CPU IP provider is the key to the development of purpose-built SoCs and faster time to market to address this enormous opportunity. The open, compact, modular and extensible RISC-V ISA together with its extensive ecosystem is the perfect choice for these embedded SoCs,” said President of Andes Technology, Frankwell Lin. ”We are thrilled to upgrade our membership to Platinum and work even closer with the RISC-V community to solve application and persistent computing challenges for the embedded ecosystem.”

“We joined the RISC-V Foundation because the RISC-V ISA aligned almost perfectly with our original self-developed ISA. Our customers can continue to use their AndeSight™ IDE (Integrated Development Environment) simply by upgrading, and we can bring our years of experience in processor IPs and embedded systems to our new RISC-V users and customers.” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “AndesCore™ runs from one to more than 1,000 cores in a single SoC in which Andes provides a wide variety of solutions to empower our customers. By upgrading to a Platinum Member Representative, we will devote more resources to the RISC-V ecosystem and continuously bring more processor solutions to market, enriching the RISC-V product line. This helps drive our vision of Taking RISC-V Mainstream.”

About Andes Technology

After 14-year effort starting from scratch, Andes Technology Corporation is now a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve the rapidly growing global embedded system applications. Andes is also a founding Platinum member of RISC-V Foundation and the first mainstream CPU vendor adopted the RISC-V as the base of its fifth generation architecture, the AndeStar™ V5. In order to meet the demanding requirements of today’s electronic devices, Andes delivers highly configurable and performance-efficient CPU cores with full-featured integrated development environment and comprehensive software/hardware solutions to help customers innovate their SoC in a shorter time frame. Since 2018, the yearly volume of Andes-Embedded™ SoCs has surpassed the 1-billion mark. Andes Technology’s comprehensive RISC-V CPU families cover from entry-level 32-bit N22, mid-range 32-bit N25F/D25F/A25 and 64-bit NX25F/AX25F, to the high-end multicore A(X)25MP.

For more information, please visit https://www.andestech.com

Secure-IC and Andes Technology jointly provide cybersecurity enhanced RISC-V cores

Post author:Sheila
Post published:2019-11-13
Post category:Press Release

【Hsinchu, Taiwan】– November 13, 2019 – Today, Secure-IC, the embedded security solutions provider from France specialized in embedded cybersecurity to protect against attacks, enters a strategic partnership with Andes Technology Corporation (TWSE: 6533), a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 1-billion diversified SoCs yearly. This strategic partnership consists in delivering a secure high performance processor. Secure-IC’s Cyber Escort Unit™ associated with Andes RISC-V processors ensures a protection against both Physical and Cyber Attacks such as buffer overflow, fault injection attack, instruction skip or replacement and is compliant with high security levels (EAL) regarding the Common Criteria Certification and the PP0084 Protection Profile. In addition, the solution is fully aligned with the DARPA System Security Integrated Through Hardware and Firmware (SSITH) program.

AndesCore™ RISC-V processors, based on AndeStar™ V5 architecture, currently include the ultra-compact 32-bit N22 for entry-level microcontrollers and deeply-embedded protocol processing, the 32/64-bit N25F/NX25F for high-speed control tasks or floating-point intensive applications, the 32-bit D25F for signal processing applications, the A25/AX25 for Linux-based applications and the A25MP/AX25MP for cache coherence multi-core applications. To make them best fit application requirements, the 25-series processors offer optional key features such as dynamic branch prediction, instruction and data caches, local memories, floating point unit, and DSP extension. Leveraging its long track record of CPU technologies, Andes delivers its RISC-V processors with leading performance efficiency, and many advanced features such as StackSafe™ for hardware stack protection, CoDense™ for code size compression, and PowerBrake for power management. Moreover, Andes RISC-V cores are available with a rich set of system level configuration options such as Physical Memory Protection (PMP) and Platform-Level Interrupt Controller (PLIC).

The Secure-IC’s Cyber Escort Unit is designed to fill the security gap between software cybersecurity and hardware by escorting step by step the program execution to achieve high execution performance in a secure way, allowing real-time detection of zero-day attacks. Unique on the market, this product builds the foundation for hardware-enabled cybersecurity. It is the only tool on the market that comprises technologies for detecting and deceiving cyberattacks. This technology acts on-the-fly. Precisely, Cyber Escort Unit (Cyber EU in short) is a two-fold technology aiming to protect against four threats:

Return oriented programming (ROP), Jump Oriented Programming (JOP): The attacker reuses chunks of code to assemble a malicious program as a patchwork.
Stack Smashing, by exploiting a buffer overrun or integer under-or-overflow etc.: the attacker crafts some fake stack frames in order to change the program context.
Executable Code Modification, overwrite: the attacker manages to change the genuine program into a malicious program.
Control Flow hijacking: the attacker manipulates the program so that it calls an illicit function, or it takes an illicit branch.

Secure-IC’s solution is deterministic in timing and suitable for real-time application, such as mission-critical applications (e.g., safety requirements in automotive industry) & also suitable for cyber-physical systems, i.e., detecting issues irrespective they arise from physical alteration or cyber-attack.

“Cybersecurity becomes a real challenge because there are many connected devices, and attackers are becoming more and more destructive,” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “We are very pleased to work with Secure-IC to provide the excellent cybersecurity solution to help our customers design robust IoT SoCs. With the integrated platform and FPGA demo ready solution of industry-leading Cyber Escort Unit from Secure-IC and the RISC-V processors from Andes, SoC designers can easily prevent hostile attacks from the outside world with outstanding performance and network security.”

Secure-IC CEO, Hassan Triqui said, “It is a pleasure to integrate our Cyber Escort Unit solution with Andes RISC-V processor. The integration of Cyber Escort Unit with Andes solution provides to customer a secure and high performance processor that protects the systems against security and safety threats. ”

Secure-IC flagship IP is the “Securyzr”, a root-of-trust solution for ensuring device security and offering security services (such as authentication, life cycle management, remote configuration and cloud on boarding). This security subsystem can embed a dedicated processing unit based on a standard or cybersecurity-enhanced AndesCore™ V5 processor. The Securyzr using Cyber Escort Unit-security enhanced AndesCore offers a resilience against various attacks such as Side Channel Attack, Fault Injection Attack and Cyber Attack.

About Andes

After 14-year effort starting from scratch, Andes Technology Corporation is now a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve the rapidly growing global embedded system applications. Andes is also a founding member of RISC-V Foundation and the first mainstream CPU vendor adopted the RISC-V as the base of its fifth generation architecture, the AndeStar™ V5. In order to meet the demanding requirements of today’s electronic devices, Andes delivers highly configurable and performance-efficient CPU cores with full-featured integrated development environment and comprehensive software/hardware solutions to help customers innovate their SoC in a shorter time frame. Since 2018, the yearly volume of Andes-Embedded™ SoCs has surpassed the 1-billion mark. Andes Technology’s comprehensive RISC-V CPU families cover from entry-level 32-bit N22, mid-range 32-bit N25F/D25F/A25 and 64-bit NX25F/AX25F, to high-end multicore A(X)25MP.

For more information, please visit https://www.andestech.com

About Secure-IC

Secure-IC has established a thought leadership position in the security world.

Secure-IC sets itself apart by accompanying customers along the IC design process by providing best in class protection embedded Secure Elements and security IP cores, security evaluation solutions & consulting services to reach the best available certification required for different markets.

Combining a full set of analysis platforms with best of breed set of security technologies & backed by almost 40 families of international & global patents, Secure-IC is considered a leader in cyberspace security embedded systems. Secure-IC protects companies against attacks and guarantees at each stage of the design process that an optimal security level is reached. The best of breed technologies that are provided stem from the company’s commitment to the research community, as a spin-off from Telecom Paris Tech University, in order to foresee future major threats, tackle problems with innovative solutions & empower the intricate work of the industry standardization bodies. The company provides Silicon proven technology, pioneering in AI for embedded security, post quantum & hybrid, and state-of-the-art synthesis of attacks/ countermeasures. The embedded security system lines can be better recognized as Threat Protection (A combination of smart units & expertise results), Threat Analysis (Ready to use, pre & post silicon & SW analysis platforms) and Think Ahead (the next steps towards all security challenges).

For more information about Secure-IC solution, click http://www.secure-ic.com