Andes Technology and Tiempo Secure Announce Strategic Partnership to Enhance RISC-V Platform Security up to CC EAL5+ Certification

HSINCHU (Taiwan) and GRENOBLE (France) , October 1st, 2019 Andes Technology Corporation, a leading supplier of outstanding efficiency, low-power, high performance 32/64-bit embedded CPU cores, including a broad family of RISC-V cores, has entered into a strategic partnership with Tiempo Secure, a unique supplier of ISO/IEC 15408 standard CC (Common Criteria) EAL5+ (Evaluation Assurance Level) grade secure element IP, to bring the RISC-V based security solution up to CC EAL5+ certification.

The rise of IoT is driving serious concern about security, including at the edge device level. According to recent Ericsson research, by 2024, there will be more than 22 billion connected IoT devices. While security based from separation mechanism is commonly deployed, it is admitted that there is some limitation in term of security certification. Furthermore, security integration into the IoT ecosystem could become complex.

The alternative is to enable security from a tamper resistant and certified hardware as a security enclave (Secure Element IP) into the MCU or SoC design.

Tiempo Secure has developed a Secure Element IP (TESIC) as a hard macro integrating CC EAL5+ grade state-of the-art security countermeasures and security sensors against side channel and intrusion attacks. The integration of this Secure Element IP into a RISC-V SoC will bring the security of this SoC up to CC EAL5+ security, without compromising on power consumption.

“Andes Technology offers RISC-V based ultra-compact processor with the outstanding performance and low power consumption available on the market,” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “Integrating Tiempo Secure’s CC EAL5+ security enclave into AndesCore N22 solution will now allow our customers to address the most security critical applications on the IoT market.”

“By working with Andes Technology we’re able to dramatically enhance the security that developers need to protect their IoT ecosystems based on RISC-V,” said Serge Maginot, CEO of Tiempo Secure. “The plug-and-play integration of TESIC, our CC EAL5+ grade Secure Element IP, into the RISC-V cores of Andes Technology will enable RISC-V developers to easily integrate certified security features, such as secure boot, secure firmware update or iUICC stack, into their system.”

Once the Secure Element IP from Tiempo Secure is embedded into the RISC-V based AndesCore N22 designed by Andes Technology, the whole system can pass the highest level of security certification, including CC EAL4+/EAL5+ PP0084 and FIPS 140-2. It also solves the problem of security integration into the IoT ecosystem.

About Andes Technology

Andes Technology Corporation is a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve the rapidly growing global embedded system applications. The company delivers superior low power CPU cores, including the comprehensive RISC-V V5 family of processor cores, with integrated development environment and associated software/hardware solutions for efficient SoC design. Up to the end of 2018, the cumulative volume of Andes-Embedded™ SoCs has reached 3.5 billion with 2018 alone contributing over 1 billion. Andes Technology’s comprehensive CPU line includes entry-level, mid-range, high-end, extensible and security families. For more information, please visit www.andestech.com

About Tiempo Secure

Tiempo Secure is an independent company founded by semiconductor industry experts having unique experience in the development of secure microcontrollers and embedded secure software. The company has already designed and certified Common Criteria EAL5+ and EMVCo secure microcontroller chips, available in contact and dual interface mode, for Government ID and High-end Banking applications. Tiempo Secure is now offering CC EAL5+ proven/certification-ready Secure Elements for the IoT market, either as companion chips or as hard IP macros that are easy to integrate into application/SoC chips, allowing the customer chips to pass CC EAL5+ and other security standard certification.

The company is headquartered in Montbonnot, near Grenoble, France. More information can be found at www.tiempo-secure.com

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Andes and Dover Microsystems Partner to Deliver Professional Network Security Solution for RISC-V

HSINCHU, TAIWAN , Sept. 25, 2019 – Andes Technology Corporation (TWSE: 6533), a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 1-billion diversified SoCs yearly, and Dover Microsystems, the first company to immunize processors against entire classes of network-based attacks, announced a strategic partnership to deliver professional network security solution for RISC-V. Dover’s CoreGuard® technology is the only solution for embedded systems that prevents the exploitation of software vulnerabilities. Dover’s CoreGuard silicon IP integrates with Andes RISC-V processors to protect against 94% of known software vulnerabilities, including 100% buffer overflows, code injection, and data exfiltration as well as safety violations.

Andes RISC-V processors are based on AndeStar™ V5 architecture, which maintains the full compatibility to RISC-V technology and thus inherits its compact, modular and extensible advantages. In addition, AndeStar V5 architecture brings Andes-extended features already proven in high-volume V3 AndesCore™ processors to be effective and beneficial to embedded applications with enhanced performance, code size and development support. Andes RISC-V cores include ultra-compact 32-bit N22 for applications such as entry-level microcontrollers and deeply-embedded protocol processing, 32-bit D25F for signal processing applications, 32/64-bit N25F/NX25F for high-speed control tasks or floating-point intensive applications, A25/AX25 for Linux-based applications and A25MP/AX25MP for cache coherence multi-core applications.

Dover Microsystems’ CoreGuard silicon IP acts as a bodyguard to the host processor, monitoring every instruction executed to ensure that it complies with a defined set of security, safety, and privacy rules – called micropolicies – that precisely define allowed versus disallowed behavior. CoreGuard maintains micropolicy-relevant metadata about every word in memory, and then uses this metadata to crosscheck each instruction processed against the installed set of micropolicies. If an instruction violates any micropolicy, CoreGuard Policy Enforcer hardware stops it from executing before any damage is done. CoreGuard Policy Enforcer RTL is licensed and delivered as a set of hardware SystemVerilog design files. Dover includes the base set of CoreGuard micropolicies that protect all embedded systems.

“Andes is determined to provide the best RISC-V solutions to help our customers design SoC exceeding their expectations. We understand that network security is a major concern of many IoT applications,” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “With the pre-integrated, verified solution of industry-leading CoreGuard technology from Dover Microsystems and the leading performance-efficient RISC-V processors with rich features for embedded systems from Andes Technology, SoC designers gain quick access to a mature RISC-V solution with outstanding performance and network security.”

“Our CoreGuard silicon IP integrates with existing RISC processors to protect embedded systems against security, safety, and privacy threats,” said Jothy Rosenberg, Founder and CEO of Dover Microsystems. “The integration of CoreGuard with the high-quality AndesCore RISC-V processor is clean and straightforward, providing customers with the most powerful and easy to adopt security solution that immunizes SoCs against network-based cyberattacks.”

For more information about Andes RISC-V processors, click http://www.andestech.com/markets.php.
For more information about Dover Microsystems CoreGuard®, click https://www.dovermicrosystems.com/solutions/coreguard

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