Andes certifies Imperas RISC-V Reference Models for the new RISC-V P (SIMD/DSP) extension

Imperas simulation technology and RISC-V reference models updated to cover the RISC-V P Extension for SoC architecture exploration and early software development

Andes Certifies Imperas RISC-V Reference Models For The New RISC-V P (SIMD/DSP) Extension

Oxford, United Kingdom, July 12th, 2021 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced that Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V CPU cores and a Founding Premier member of the RISC-V International Association, has certified the Imperas reference models for the complete range of Andes IP cores with the new RISC-V P extension. Developers can now use the Imperas reference models to evaluate multicore design configuration options for SoC architecture exploration.

The open standard RISC-V ISA (Instruction Set Architecture) has a modular structure based on multiple independent extensions that offer dedicated and enhanced functionality to optimize a processor for the target application. The new SIMD/DSP extension, designated as ‘P’ in the specification description, supports efficient data processing applications and real-time requirements. The RISC-V International P Extension Task Group is in the final stages of submitting the specification to the official ratification process, which is expected to be completed within H2 2021.

The Imperas simulation technology enables fast and accurate virtual platforms that are central to modern SoC design and embedded software development. Working with lead customers, the Imperas models of the Andes cores have already been used for commercial projects, which are now implemented in silicon.

Optimizing a multicore design is one of the most challenging design tasks. Multiple independent processing units interacting with each other plus shared peripherals together with real-time processing tasks supporting a mix of OS/RTOS running firmware and application software. SoC architecture exploration allows a full evaluation of software running before the final decision and configuration of the hardware options. These virtual prototypes also support early software development, often many months before silicon prototypes are available. For final software testing, a virtual platform allows the actual binary code to be verified with access and visibility not available in real hardware or without compromising the software under test with additional test code.

“RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations,” said Dr. Charlie Su, President and CTO at Andes Technology Corp. “The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.”

“Embedded development depends on the optimized balance between hardware resources and software applications,” said Simon Davidmann, CEO at Imperas Software Ltd. “With the Imperas golden reference models, developers can explore full software development for all the Andes cores, including the new RISC-V P extension and Andes ACE custom instructions.”


About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020, and the cumulative volume has reached 7 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook and YouTube!

About Imperas
Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multicore systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

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Andes Technology and Rambus Collaborate to offer Secure Solution for MCU and IoT Applications

HSINCHU CITY, TAIWAN – February 24, 2021 – Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced a collaboration with Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, to develop a complete low-power, size-optimized secure solution for Microcontrollers (MCUs) and Internet of Thing (IoT) applications.

According to Statista, the total number of connected IoT devices will grow to 21.5B units by 2025. As the IoT market has exploded, consumers and governments alike are demanding that device and data security requirements are a primary design requirement for all IoT devices. Accordingly, IoT device makers are increasingly demanding that MCUs be secure by design, offering “out of the box” security. To address these needs, Andes and Rambus are collaborating to offer a secure solution for MCUs embedded with Andes RISC-V -based CPU and Rambus Security Root of Trust. The Rambus Root of Trust securely boots the MCU, protects the device identity and offers authentication, secure debug, and other cryptographic services to the host system. All AndesCore™ RISC-V processors optimally leverage Rambus Root of Trust to offer these security services and reduce power for compute-intensive cryptographic operations.

“Today, security has been a fundamental and mandatory feature for IoT devices required by markets, consumers, and governments,” said Dr. Charlie Su, Andes Technology CTO and EVP. “To fulfill the requirements of different security levels, we are very pleased to collaborate with Rambus to provide an optimized secure solution for microcontrollers. With the integrated platform and FPGA ready solution of Rambus Root of Trust and Andes RISC-V processor IPs, SoC vendors can focus on their core value, key competitive and unique differentiation. They don’t need to worry about protecting the system against security threats.”

“As the connected device market continues to expand rapidly, the security of valuable assets and services is a primary concern for users and manufacturers alike,” said Gijs Willemse, senior director of product management, Rambus Security. “This collaboration will provide a strong and low-power security foundation for MCUs. It allows manufacturers to assure their customers that devices will function without the worry of security breaches that risk user privacy or interrupt their cloud services.”

AndesCore™ RISC-V processors, based on AndeStar™ V5 RISC-V architecture, consists a series of high efficiency and low power 32-bit/64-bit CPU core families range from the entry-level N22, mid-range 25-series, advanced 27-series to high-performance superscalar 45-series. Andes RISC-V vector processor NX27V is designed for broad market segments of today’s computation-intensive applications. Andes Custom Extension™ framework empowers customers to innovate Domain-Specific Acceleration via creating new instructions. AndesCore RISC-V processors have been used in a wide variety of SoCs ranging from microcontrollers to data center servers, and from edge to cloud applications. 

Providing a hardware-based foundation for security, Rambus offers a catalog of robust Root of Trust solutions, ranging from richly featured military-grade co-processors to highly compact state machines. With a breadth of solutions applicable from the data center to Internet of Things (IoT) devices, Rambus has a Root of Trust solution for almost every application.

About Andes Technology
Andes Technology (TWSE: 6533) was established in Hsinchu Science Park in 2005. Sixteen years in business and a founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020. Up to the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has reached 6 billion.

About RISC-V AndesCore™
Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, A25MP/AX25MP, A27/AX27/NX27V, A45/D45/N45 and AX45/DX45/NX45.

For more information about Andes Technology, please visit http://www.andestech.com/

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