Andes Technology Unveils the AndesCore™AX60 Series, an Out-of-Order Superscalar Multicore RISC-V Processor Family

The AX65, the First Member of the AX60 Series, Offers Leading Performance Based on Next-generation CPU Micro-architecture

Santa Clara, California — November 2, 2022 — Today, at Linley Fall Processor Conference 2022, Andes Technology, a leading provider of high efficiency, low power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, reveals its top-of-the-line AndesCore™ AX60 series of power and area efficient out-of-order 64-bit processors. The family of processors are intended to run heavy-duty OS and applications with compute intensive requirements such as advanced driver-assistance systems (ADAS), artificial intelligence (AI), augmented/virtual reality (AR/VR), datacenter accelerators, 5G infrastructure, high-speed networking, and enterprise storage.

The first member of the AX60 series, the AX65, supports the latest RISC-V architecture extensions such as the scalar cryptography extension and bit manipulation extension. It is a 4-way superscalar with Out-of-Order (OoO) execution in a 13-stage pipeline. It fetches 4 to 8 instructions per cycle guided by highly accurate TAGE branch predictor with loop prediction to ensure fetch efficiency. It then decodes, renames and dispatches up to 4 instructions into 8 execution units, including 4 integer units, 2 full load/store units, and 2 floating-point units. Besides the load/store units, the AX65’s aggressive memory subsystem also includes split 2-level TLBs with multiple concurrent table walkers and up to 64 outstanding load/store instructions.

AX65 supports multicore cluster with cache coherence to scale out performance. Each core has 64KB private instruction and data caches. The cluster contains up to 8 cores, an in-cluster coherence manager and a shared cache up to 8MB. Its IO coherence interface keeps all AX65 caches coherent with respect to the external IO transactions and allows ease of SoC integration. The coherence manager and the shared cache can use a clock asynchronous to the cores for overall performance optimization in SoC implementations. Moreover, AX65 supports RISC-V standard external debug and instruction trace interfaces to facilitate fast system development, analysis and debugging.

“With hundreds of licensees and billions of chips embedding AndesCore™, Andes has proved it as the CPU IP vendor to rely on. Our mission is to continue to provide a comprehensive lineup of processor IPs to support a wide range of applications from tiny MCUs to datacenter accelerators, offer efficient control processing as well as powerful compute acceleration, and run bare metal, RTOSes and Linux. We are excited to announce our top-of-the-line family of processors, the AX60 series, to further expand our portfolio. ” said Dr. Charlie Su, President and CTO of Andes Technology. “The AX65 is to offer 2x performance in large benchmarks over the previous high-end core, the AX45, at the same frequency. In addition, it is capable of operating at 2.5GHz at 7nm process, 25% over the AX45. With the great boost in performance, the AX65 processor addresses the emerging requirements of a wide range of applications looking to raise control processor performance in the current high-performance SoCs.”

The AndesCore™ AX65 is to be available for lead customers in mid-2023 through the early access program and for general customers by the end of the same year. For further information about the AX65 and the AX60 series processors, please contact Andes Technology.

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes is publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube! 

Press Contact:

Jonah McLeod

+1 (510) 449-8634

Jonahm@andestech.com

Hsiaoling Lin

+886-3-6687253 ext.644

hllin@andestech.com

Continue ReadingAndes Technology Unveils the AndesCore™AX60 Series, an Out-of-Order Superscalar Multicore RISC-V Processor Family

Andes Announces the N25F-SE Processor, the World First RISC-V CPU IP with ISO 26262 Full Compliance

Systematic failures and random hardware failures can be mitigated by development process and safety designs of the safety-enhanced N25F-SE

HSINCHU, TAIWAN – October 17, 2022 – Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, today announces its safety-enhanced AndesCore™ N25F-SE is the first RISC-V CPU IP certified to be fully compliant with ISO 26262 functional safety standards for the development of automotive applications. SGS-TÜV Saar GmbH, an independent functional safety certification body, has assessed and completed product audit process for N25F-SE with achieved functional safety for ASIL B (Automotive Safety Integrity Level B) applications, according to all applicable ISO 26262 series of standards including Parts 2, 4, 5, 8 and 9.

AndesCore™ N25F-SE. The N25F-SE is a 32-bit RISC-V CPU core that supports standard IMACFD extensions, including efficient integer instructions and single/double precision floating point instructions. It incorporates the Andes V5 extension instructions to further boost performance and reduce code size. The efficient 5-stage pipeline of the N25F-SE provides a good balance of high operating frequency and compact design. Its flexible interfaces greatly simplify SoC designs. Like its sought-after cousin the N25F, the N25F-SE comes with rich configurable options, all of which are fully certified, and thus SoC design teams are not limited by one fixed CPU configuration when offering automotive solutions.

ISO 26262 and ASIL-B Applications. ISO 26262 defines functional safety as the “absence of unreasonable risk due to hazards caused by malfunctioning behavior of electrical/electronic systems”. To enforce functional safety with a reasonable cost structure, proper safety measures for desired ASIL levels should be applied, from the least stringent ASIL A to the most stringent ASIL D. Examples of electronic systems where ASIL B is sufficient are dashboard, in-car monitoring, keyless entry, lighting control, tire pressure monitoring, vision ADAS, and window control. Either to incorporate new electronic systems on board, or to upgrade existing ones without ISO 26262 compliance, the N25F-SE is well suited for the wide range of applications requiring ASIL B compliance.

Leader of RISC-V Functional Safety. “Andes is the first RISC-V CPU vendor certified, for the development process of automotive processor cores, to be compliant with ISO 26262 standards up to ASIL D in 2020. With the certified development process in place, we formally started our functional safety roadmap to deliver at least one ISO 26262 compliant core every year to cover all segments of performance and features,” said Dr. Charlie Su, President and CTO of Andes Technology. “Andes has developed a wide range of AndesCore™ processors, from driving cost sensitive MCUs to accelerating datacenter AI/ML computations. We are excited to announce our first safety-enhanced AndesCore® the N25F-SE based on the most popular and mature CPU IP family, the 25-series.”

ISO 26262 Full Compliance. The ASIL B fully compliant N25F-SE was developed under considerations on all applicable requirements of ISO 26262 standards by defining tailored safety activities with solid rationales, from the fundamental specification, analysis, and design to verification and many more. It comes with the Safety Package which includes Safety manual, Safety analysis report (FMEDA and more), and Development Interface Outline. Together, the N25F-SE and its Safety Package offer an effective, efficient, and flexible automotive solution. It greatly reduces the time for SoC design teams to certify their ISO 26262 compliant SoCs. In comparison, an ASIL B “ready” solution is without certifying all required ISO 26262 Parts (2, 4, 5, 8 and 9) and thus provides incomplete support for the SoC’s certification; as a result, SoC design teams must go through all the work the CPU IP vendors are supposed to do. In addition, the N25F-SE helps reduce the cost and power consumption for SoCs requiring only an ASIL B processor IP without forcing them to use a double-sized dual-core lock-step solution with ASIL D. “As the only public RISC-V CPU IP company and a leader in the RISC-V ecosystem, we want to raise the awareness of the importance of ISO 26262 full compliance.” Dr. Su stressed.

  • Cidana. “Consumer experience is shaping expectations for In-Vehicle Infotainment (IVI) systems. It is one of the segments evolving rapidly in the automotive industry. Cidana offers the optimized LC3+ codec and makes it available on Andes ISO 26262 compliance platform. Other mainstream audio codecs can be supported based on the required performance,” said Chinn Chin, the Chief Executive Officer of Cidana. “We are looking forward to collaborating with Andes and bringing the Cidana solutions to automotive SoCs powered by the N25F-SE.”
  • Green Hills Software. “We are pleased to expand our production-ready automotive safety solutions to support the safety-certified AndesCore™ 25-Series RISC-V IP core family from the technology leader, Andes Technology,” said Dan Mender, Vice President, Business Development, Green Hills Software. “This combined hardware-software solution for the AndesCore™ N25F-SE gives SoC providers a valuable head-start in offering integrated and optimized production-proven platforms for next-generation vehicle ECUs that require the highest performance and lowest power, with advanced tools that reduce their customers’ time to market and development costs.”
  • IAR Systems. “RISC-V is being adopted at a remarkable speed in applications from the edge to the cloud and now it is entering the automotive market. IAR Systems support the mature and popular Andes RISC-V 25-series processors since its release a few years back in the IAR Embedded Workbench for RISC-V, Functional Safety edition. We are glad to learn that Andes N25F-SE has been certified for full ISO 26262 compliance,” said Rafael Taubinger, Sr. Product Marketing Manager at IAR Systems. “We are looking forward to extending our collaboration with Andes to support its Safety Enhanced processors starting from the N25F-SE enabling our mutual customers to speed up the path to using RISC-V in automotive safety-critical applications.”
  • Parasoft. “We would sincerely congrats on Andes Technology’s N25F-SE been certified to the ISO 26262 functional safety standard,” said Yue Liu, the President of Parasoft Greater China. “Andes is a leading provider of RISC-V processors, and PARASOFT, a solution provider that helps enterprises deliver defect-free software, is pleased to partner with Andes to further
    deliver RISC-V ecosystem solutions to our customers. I am confident that we will be able to provide a complete suite of testing solutions for the automotive safety lifecycle in the near future, helping customers improve their ability to develop and deliver high quality software.”
  • Virtual Open Systems. “At Virtual Open Systems we are working with Andes to enable hypervisor-less mixed criticality virtualization supporting concurrent execution of a certified real time operating system (OS) with a general purpose OS using our VOSySmonitoRV, a low level firmware developed with ASIL certification in mind,” said Daniel Raho, Virtual Open Systems SAS CEO. “We are excited to extend VOSySmonitoRV with support for Andes Safety Enhanced processors starting from the N25F-SE.”

The AndesCore™ N25F-SE is available for licensing now. Over half of a dozen leading SoC companies are already developing in-vehicle applications with the N25F-SE. Following the N25F-SE, the D25F-SE with DSP/SIMD extension and Bit Manipulation extension is expected to be available in early 2023.

 

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes is publicly-listed
company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit
cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annualvolume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed10 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube!

 

Press Contact:

Jonah McLeod

+1 (510) 449-8634

Jonahm@andestech.com

 

Hsiaoling Lin

+886-3-6687253 ext.644

hllin@andestech.com

Continue ReadingAndes Announces the N25F-SE Processor, the World First RISC-V CPU IP with ISO 26262 Full Compliance

Andes Technology Announces Return of the Annual RISC-V CON on October 18th in the San Jose Airport DoubleTree Hotel

RISC-V CON Features Keynotes from Andes, Intel, Sonical, Crypto Quantique, Green Hills Software and Imperas

SAN JOSE, CA – October 10, 2022—Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, announces the return of its annual RISC-V CON on October 18th in the San Jose Airport DoubleTree Hotel. The RISC-V CON program will include keynotes from Intel Foundry Services, Intel RISC-V Ventures, SoC developer Sonical, and Andes along with technical talks and panel from RISC-V ecosystem partners including Crypto Quantique, Green Hills Software, IAR Systems and Imperas.

Andes Technology President & CTO, Dr. Charlie Su, will begin the program at 10:00 AM with his presentation, “Expanding the RISC-V Horizon.” “It is no secret that RISC-V architecture is growing, its membership is rising, and the RISC-V ecosystem is flourishing,” Dr. Su observed. “All in an unprecedented speed. In my talk, I will examine the expanding range of applications RISC-V serves and how Andes RISC-V solutions help drive this open instruction set architecture’s fast adoptions. I will also talk about Andes RISC-V cores coming on the horizon.”

Keynotes from Bob Brennan, Vice President of Intel Foundry Services and Vijay Krishnan, General Manager, RISC-V Ventures of Intel will respectively address how RISC-V flourishes in a new foundry era and how Intel enables RISC-V for AIoT and edge applications. Sonical will present their next generation of hearable devices using RISC-V. In addition, RISC-V ecosystem talks from Crypto Quantique, Green Hills Software and Imperas will introduce their optimized RISC-V solutions and tools perfect for applications including IoT, functional safety, security and more.

The conference program runs from 10:00 AM to 4:05 PM with lunch and an evening reception included. During the reception, prize drawings will award personal electronics containing Andes RISC-V CPU IP to lucky attendees. Dan Nenni, founder of SemiWiki.com, the open forum for semiconductor professionals, will moderate the “RISC-V Ecosystem Panel: From Edge to Cloud“ that will begin immediately after lunch. The conference is free and it is open to qualified registrants such as design engineers, engineering managers, marketing people and business development personnel. The exhibition accompanying the conference program will showcase MPU development board from Renesas, AI development kit with camera module from Canaan, high-performance industrial-grade microcontrollers from HPMicro, Bluetooth development kit from Telink and Arduino-compatible boards containing RISC-V CPU IP as well as Sonical detailing their Headphone 3.0., the next generation of hearable devices, that unlocks untapped resource of biometric data. To register,  click https://Andes_RISC-V_CON_2022_US.eventbrite.com/?aff=PR

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube! 

 

Continue ReadingAndes Technology Announces Return of the Annual RISC-V CON on October 18th in the San Jose Airport DoubleTree Hotel

Andes Technology Corp. Announces its Contribution to the Intel Pathfinder for RISC-V

AndesCore™ AX45MP 64-bit Multicore Processor and NX27V 64-bit Vector Processor, Both with AXI-based AE350 Platform, Are Available in Intel® FPGA Based Pre-silicon Development Tools.

SAN JOSE, CA – August 30, 2022 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, reveals its contribution to the Intel® Pathfinder for RISC-V* for pre-silicon development initiative today.  Andes announced its highly sought 64-bit superscalar multicore AX45MP processor IP and 64-bit vector processor core NX27V with up to 512-bit vector length, both pre-integrated with AXI-based AE350 platform, have been made available in the Intel® Stratix® 10 GX FPGA Development Kit.

“Those two popular RISC-V CPU cores on Andes IP offerings address the requirements of many high-end applications,” said Frankwell Lin CEO of Andes Technology Corp. “Examples are datacenter AI accelerators, storage for enterprise, 5G networks, and AR/VR. By having those two cores available in the Intel® Stratix® 10 GX FPGA Development Kit, SoC design teams can boot Linux OS or upload their critical compute kernels to the FPGA board to quickly explore the benefits of AX45MP and NX27V before first silicon. We are extremely proud of Andes’ contribution to the Intel Incubation & Disruptive Innovation (IDI) Group’s initiative to streamline development flow to leverage Intel Foundry Services state-of-the-art fabs.”

“With Andes Technology Corp. enabling their IP for Intel Pathfinder, SoC designers can easily run interesting software code before finalizing their RISC-V designs,” said Vijay Krishnan, GM, RISC-V Ventures, Intel Corporation. “Intel is committed to accelerating the adoption of RISC-V through a unified, open and standards-based approach.”

To start your journey with Intel Pathfinder for RISC-V, please visit pathfinder.intel.com

* Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion since 2021 and continues to rise. In the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion.

For more information, please visit  http://www.andestech.com/en/homepage/. Follow Andes on Twitter, LinkedIn, YouTube and Facebook.

Andes Technology Media Contact:

Jonah McLeod

Phone: +1-510-449-8634

E-mail: Jonahm@andestech.com

Continue ReadingAndes Technology Corp. Announces its Contribution to the Intel Pathfinder for RISC-V

Andes Technology and Green Hills Software Team Up to Deliver Advanced Automotive Safety Platform for RISC-V

Collaboration brings together the ISO 26262 to-be-certified AndesCore™ N25F-SE with Green Hills automotive safety solutions to support a wide range of automotive applications that require safety, security, and efficiency.

SANTA BARBARA, CA — August 17, 2022 — Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading RISC-V CPU IP vendor and a Founding and Premier member of RISC-V International, and Green Hills Software, the worldwide leader in embedded safety and security and a member of RISC-V International, today announced their collaboration to offer an integrated and optimized platform for safe and secure computing on the AndesCore™ 25-Series family of RISC-V cores from Andes Technology. The comprehensive software offering from Green Hills Software will include the safety-certified µ-velOSity™ real-time operating system (RTOS), the ASIL-certified MULTI® development environment with advanced system-level debugging and analysis tools and C/C++ Optimizing Compilers, along with the Green Hills Probe for JTAG and trace target connections.

The combined hardware and software platform from Andes Technology and Green Hills Software is designed for SoC companies and end-customers to create market-leading 32/64-bit RISC-V-based SoCs targeting critical functions requiring ISO 26262 ASIL B to ASIL D, making the combined platform ideal for vehicle electronics requiring compact and cost-sensitive SoCs that are still capable of ASIL certification.

Andes Technology is the first RISC-V processor IP vendor to receive ASIL D process certification for both hardware (ISO 26262-5) and software (ISO 26262-6). Andes Technology is committed to supporting automobile professionals in developing safety-related product lines. The functional safety-enabled solution Andes Technology and Green Hills Software are offering is expected to be available for general licensing by the second half of 2022.

“AndesCore RISC-V processor IP with safety enhancement has already been adopted by several early customers due to its unique and competitive value,” said Dr. Charlie Su, Andes Technology President and CTO.  “The exciting partnership with Green Hills Software enables us to further offer comprehensive and robust development support for our customers. We welcome the benefits that Green Hills Software’s mature functional safety solutions bring to the RISC-V community to speed up the adoption of RISC-V safety-related applications.”

“We are pleased to expand our production-ready safety solutions support to include the latest advanced safety-certified RISC-V AndesCore™ IP from technology leader, Andes Technology,” said Dan Mender, Vice President, Business Development, Green Hills Software. “And with this combined hardware-software solution, SoC providers utilizing the AndesCore™ 25-Series family can immediately start developing their next generation vehicle ECUs with the highest performing, lowest power offerings, while reducing their customers’ time to market and development costs by offering integrated and optimized production-proven solutions.”

The combined hardware and software platform from Andes Technology and Green Hills Software features the following:

  • The AndesCore™ 25-Series RISC-V Family: Andes Technology’s AndesCore™ 25-Series is a family of 32/64-bit CPU IP cores based on AndesStar™ V5 architecture incorporating RISC-V technology. Its 5-stage pipeline is optimized for high operating frequency and high performance, yet with a small gate count. The 25-Series supports optional single- and double-precision floating point instructions. It also offers branch prediction for efficient branch execution, instruction and data caches, local memories for low-latency accesses, and ECC for L1 memory soft error protection. Multiple power management settings enable efficient energy consumption. Andes Technology’s N25F-SE, a member of the 25-Series family, is being certified at ASIL-B in the final stage.
  • The µ-velOSity RTOS: Green Hills Software’s µ-velOSity RTOS is an ideal companion for the AndesCore™ 25-Series processors because of its small footprint, quick boot times, and optional support for multiple cores and ASIL certification. µ-velOSity is also a perfect complement to the traditional use of AUTOSAR Classic in that it can cover a different class of applications, memory footprint, performance, and features.
  • The MULTI IDE: Used by thousands of developers for over three decades, Green Hills Software’s MULTI IDE is the industry’s unrivaled integrated development environment used to create, debug, and optimize code for embedded processors. With MULTI, developers can easily see and fix difficult bugs, pinpoint performance bottlenecks, and prevent future problems. MULTI provides whole-toolchain support for custom RISC-V instructions and delivers ISO 26262 ASIL-certified C/C++ compilers and run time libraries.
  • The Green Hills Probe: The Green Hills Probe provides JTAG and high-speed trace connections to targets for multicore hardware bring-up, low-level debugging, and trace-powered analysis tools.
  • Guidance and Training: Through design guidance and training, Green Hills Software’s services teams help customers achieve their own tailored levels of safety, security, and performance, with the highest developer productivity.

 

About Green Hills Software

Founded in 1982, Green Hills Software is the worldwide leader in embedded safety and security. In 2008, the Green Hills INTEGRITY-178 RTOS was the first and only operating system to be certified by NIAP (National Information Assurance Partnership comprised of NSA & NIST) to EAL 6+, High Robustness, the highest level of security ever achieved for any software product. Our open architecture integrated development solutions address deeply embedded, absolute security and high-reliability applications for the military/avionics, medical, industrial, automotive, networking, consumer and other markets that demand industry-certified solutions. Green Hills Software is headquartered in Santa Barbara, CA, with European headquarters in the United Kingdom. Visit Green Hills Software at https://www.ghs.com.

Green Hills, the Green Hills logo, µ-velOSity and MULTI are trademarks or registered trademarks of Green Hills Software LLC, in the U.S. and/or internationally. All other trademarks are the property of their respective owners.

About Andes Technology

As a Founding Premier member of RISC-V International, Andes is publicly listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndesStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube!

Green Hills Software Media Contact:

Christopher Smith

Phone: +1-805-965-6044

E-mail: media@ghs.com

Andes Technology Media Contact:

Jonah McLeod

Phone: +1-510-449-8634

E-mail: Jonahm@andestech.com

Continue ReadingAndes Technology and Green Hills Software Team Up to Deliver Advanced Automotive Safety Platform for RISC-V

Andes Technology RISC-V Processors Reveal Outstanding Performance and Efficiency in MLPerf Tiny

HSINCHU, TAIWAN – July 20, 2022 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, submits MLPerf Tiny v0.7 benchmark for Andes V5 RISC-V processors, including the AndesCore™ D25F and D45 (with DSP/SIMD Extension) and AndesCore™ NX27V (with Vector Extension). The MLPerf Tiny benchmark suite is intended for the lowest power devices and smallest form factors, such as deeply embedded, intelligent sensing, and internet-of-things applications. The remarkable out-of-box results reveal the outstanding Andes processor capabilities with performance and power consumption.

The out-of-box results of the MLPerf Tiny v0.7 are enabled by high-performance AndesCore™ and the enhanced “TensorFlow Lite for Microcontroller” with “Andes NN Library”. AndesCore™ V5 processors with DSP/SIMD (P draft) and Vector (V) Extensions are designed for applications needing highly efficient or intensive data computation. RISC-V DSP/SIMD Extension (RVP) efficiently addresses the requirements of low-volume data computation with straightforward hardware implementation for low power consumption without handcraft optimization in the model and software package. According to the Visual Wake Words and Image Classification scores, at the same 200MHz, Andes V5 RVP cores can deliver 11 fps on the D25F and 15 fps on the D45F while typical MCUs are only capable of 6-7 fps. By providing the compact and efficient SIMD and DSP capabilities, the D25F and the D45 processors form a very comprehensive and competitive basis for the TinyML, AIoT, and signal processing applications on edges and endpoints. RISC-V Vector Extension (RVV) targets high-volume data computation. No matter in the edge or cloud, the NX27V processor provides scalable, efficient, and powerful compute capabilities for general AI, NN, and data processing applications. Moreover, “Andes NN Library” dramatically speeds up the development of Neural Network algorithms with 17.3x speedup of MobileNet-v1 INT8 using AndesCore™ NX27V with the 128-bit vector configuration over the same core executing only RISC-V baseline (scalar) instructions.

“AndesCore™ RISC-V processors make intelligence available for TinyML or MCU AI without needing extra cost for hardwired accelerators. It also could be part of an efficient AI subsystem along with an accelerator to offload unstructured computation or pre-/post-processing. It brings unique and competitive value to the customers,” said Dr. Charlie Su, Andes Technology President and CTO. “AndesCore™ processors with RVP and RVV offer comprehensive solutions to the demand for computing in every aspect. In addition, with the optimized compute libraries and tools for RVP and RVV, customers could accelerate the development with highly competitive solutions to facilitate AI applications for a wide variety of products.”

 

About Andes Technology

As a Founding Premier member of RISC-V International, Andes is publicly listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion.

For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube! 

Continue ReadingAndes Technology RISC-V Processors Reveal Outstanding Performance and Efficiency in MLPerf Tiny