AXI Fabric Package for Scalable SoC Applications

General Description

AndeShape AE300 is an AXI fabric including an AXI bus matrix and a list of auxiliary interconnect IPs. The highly configurable and scalable AXI components can be easily integrated to construct the demanded AXI interconnect fabrics and optimize for best performance-area results. A separate example platform product (AE300EP) provides a pre-integrated AXI reference platform containing AE300 IPs as well as additional peripheral IPs. This package enables users to build high flexibility, low cost, and fast time-to-market AXI systems with supported AndesCore CPU IPs.


Block Diagram

AE300–AXI Fabric: an AXI interconnect example
AE300EP –Example Platform

Feature Highlight

AE300–AXI Fabric

  • AXI bus matrix
    • Compliant with AMBA AXI4
    • Configurable connectivity between masters and slaves
    • Round-robin or 2-level priority arbitration
  • AXI interconnect
    • Support AMBA AXI4/AHB/AHB-Lite

AE300EP–Example Platform

  • AXI bus matrix
    • 32-bit address and 64-bit data width
  • ​​AHB/APB bus interconnect​​
    • 32-bit address and 32-bit data width
  • ​​APB peripherals: GPIO, PIT, SPI, UART, WDT
  • ​​Supported AndesCore processors
    • N1337/D1088/N1068A (License Separately)

Development Tools

  • IDE/Toolchain
    • AndeSight™
    • Andes BSP
  • ​​FPGA Development Board
    • AndeShape™ADP-XC7KFF676
  • Debugging Tool
    • AndeShape AICE-MCU/AICE-MINI
    • J&D CodeViser
    • Lauterbach Trace32