Andes Releases AndeSight™ IDE v5.1 to Simplify Software Development for RISC-V Heterogeneous Multiprocessor and AI


Press Highlights:

  • AndeSight™ IDE v5.1 has been released in Q1 2022
  • Key features: the first RISC-V SMP Zephyr™ RTOS, OpenAMP support, heterogeneous multiprocessor debugging, scripting automation, AndesClarity™ processor pipeline visualizer and analyzer, optimized compute libraries for AI and IoT applications for using RISC-V DSP/SIMD and Vector extension, auto-vectorization, and Andes Neural Network (NN) Library

Developing Applications on Heterogeneous Multiprocessors Using the Powerful AndeSight™ IDE Tools
AndeSight™ IDE v5.1 brings the power of application development, debugging, and analysis to the heterogeneous RISC-V multiprocessors, including the cutting-edge Andes RISC-V Superscalar Multicore A(X)45MP and Andes RISC-V Vector Processor NX27V. To support OS with SMP (Symmetric Multiprocessing), besides Linux SMP which has been well supported in RISC-V upstream and Andes platforms, Andes offers the first RISC-V port for SMP Zephyr™ RTOS and Zephyr’s driver subsystem. It has been verified on Andes RISC-V multicore platform. Developers only need to focus on the applications themselves without worrying about the underlying system software. As to AMP (Asymmetric Multiprocessing) demands, AndeSight™ integrates the OpenAMP which provides communication infrastructure between heterogeneous systems and enables AMP applications to leverage parallelism offered by multiprocessor systems.

AndeSight™ provides the user-friendly multicore debugging feature for both SMP and AMP systems in one IDE interface. To further enhance the ultimate debugging efficiency for multiprocessors, it offers a handy feature “Core Grouping” by sending debug commands to a set of cores in the same debug session. AndeSight™ also offers the record-and-replay scripting capability to save interactive steps for easy issue reproduction and automatic testing.

Accelerating AI Computations with RISC-V DSP/SIMD Extension (RVP), RISC-V Vector Extensions (RVV), Auto-vectorization, the Tools and Runtime from AndeSight™ IDE
The RVP extension enables multiple data in integer registers to be processed in one single cycle, thus efficiently boosting the performance with low power consumption for TinyML®, AIoT, and signal processing applications on edge and endpoint. Moreover, the RVV extension targets high-volume data computations with a configurable vector processing architecture; therefore, it provides scalable, efficient, and powerful compute capabilities for AI, NN, and data processing applications in edge and cloud computing.

To simplify the software development and unleash the potential of powerful ISA extensions, AndeSight™ offers full support from toolchains for RVP and RVV, their respective intrinsic functions, highly optimized DSP and Vector libraries, and sample codes to guide code optimization. Moreover, AndeSight™ IDE v5.1 enables auto-vectorization to generate RVV instructions automatically by the compiler. With the above support from AndeSight™, software developers can fully utilize the vector computing power in the C language.

To achieve the ultimate performance of a sophisticated vector processor like AndesCore™ NX27V, a processor pipeline analyzer is needed to help developers exploit the full capabilities of processors. AndesClarity™ visualizes the pipeline execution and resource bottleneck. Developers could discover stall bubbles, reasons to stall, and data dependencies associated with the instructions, the C source code, and hardware functional units for further optimization.

In addition, users could dramatically speed up the development of Neural Network algorithms with the AndeSoft™ NN Library. The NN library is optimized for RVP and RVV instructions for INT8 and FP16 data types. It also supports several quantization methods: shift-based, symmetry, and asymmetry. For MobileNet-v1 inference using NN library with FP16 data type, the NX27V processor with 512-bit SIMD width and 512-bit vector length achieves a 96x speedup over itself executing only RISC-V baseline extensions. Moreover, TensorFlow Lite for Microcontroller can execute TensorFlow models with AndeSoft™ NN Library on development boards.

AndeSight™ facilitates and streamlines the development of embedded systems and provides customers with a versatile integrated environment, including outstanding toolchains and libraries, scripting for automated operations, AndeSim™ near cycle simulator, handy analysis tools, and OS awareness development. Moreover, AndeSight™ provides abundant reference codes that enable developers to get started easily.

“We are delighted to see the arrival of the AndeSight™ IDE v5.1. It simplifies software development with handy features and optimized tools and helps accelerate the completion of highly competitive products,” said Andes President and CTO Dr. Charlie Su. “Processors cannot deliver their full capabilities without the matching software solutions. With comprehensive AndeSight™ IDE, customers can release their software with more features, better performance and higher quality in a shorter time.”

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About Andes Technology
Seventeen years in business and a Founding Premier member of RISC-V International, Andes is publicly listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. For more information, please visit Follow Andes on LinkedInTwitterFacebook, and YouTube

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