Andes Announces over 1.2 GHz RISC-V Cores Series at 28nm: A25/AX25 and N25F/NX25F


Andes Technology Corporation (TWSE:6533), a founding member of the RISC-V Foundation and the leading Taiwan-based supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 2.5-Billion SoCs covering a wide range of applications, today announced the availability of the latest four members of the AndeStar™ V5 high efficiency processor series: (1) the AndesCore™ A25/AX25, perfect for Linux-based applications such as UAV(Unmanned Aerial Vehicle), smart wireless communication, networking, video processing, ADAS (Advanced Driver Assistance Systems), storage, data center, and machine/deep learning; and (2) the AndesCore™ N25F/NX25F, that can be used for a wide range of floating-point intensive applications including advanced motor control, satellite navigation, high-precision sensor fusion, and advanced smart meters.

The A25/N25F are 32-bit CPU IP cores, and AX25/NX25F are 64-bit ones. All of them are capable of operating over 1.2 GHz at the worst-case corner of TSMC 28nm HPC+ process, delivering over 3.5 CoreMark/MHz, and 1.3 MWIPS/MHz for single precision floating point. Their common features include dynamic branch prediction, instruction and data caches, Local Memories for low-latency accesses, L1 memory ECC for soft error protection, and Andes Custom Extension™ (ACE) to greatly simplify instructions design for Domain-Specific Acceleration (DSA). All cores support User/Machine Mode (U/M mode) while the A25/AX25 add Supervisor Mode (S-mode) and memory management unit (MMU) to run Linux kernel and its applications. In the floating point side, the N25F/NX25F support IEEE754-compliance with either single precision or single/double precisions. Andes further extends floating-point support to half precision for applications such as machine learning, where loads/stores automatically convert 16-bit half-precision data to/from single precision data. The A25/AX25 also optionally support all the floating-point features mentioned above. All processors are offered in human-readable and tool-friendly Verilog RTL and with a GUI tool for designers to flexibly choose their final configurations.

“Andes adopted RISC-V as the subset of its fifth generation architecture, the AndeStar™ V5, and brings it to the RISC-V community,” Dr. Charlie Su, CTO and Senior VP of Andes Technology commented, “The A25/AX25 and the N25F/NX25F are versatile processors with a 5-stage pipeline and RISC-V compliant ISA (RV-IMAC[FD]). All 25-series processors include Andes-enhanced Platform-Level Interrupt Controller (PLIC) with vectored interrupt dispatch and priority-based preemption for efficiently serving various types of system events, and can be pre-integrated with 64-bit AXI or 64/32-bit AHB bus platforms. They also bring to RISC-V common cache features for embedded systems such as finer-grained cache management, write-back and write-through modes, and uncached accesses. In addition, PowerBrake, QuickNap™ and WFI (Wait for Interrupt) operation together enable various power modes to address application needs; JTAG and 2-wire interfaces are available for debug and trace support; the StackSafe™ protects the software stack from overflow and underflow; and the Andes’ patented CoDense™ enhances code density on top of RISC-V C-extensions. It also supports misaligned memory accesses directly in hardware, which is good for porting existing software from ARM and x86; without it, more than 100 cycles may be required in the exception handler. They have been selected by our customers for their exceptional performance/power, flexible configurations, highly optimized compiler and comprehensive development tools. We are also engaged with 3rd party partners to provide more development tools, IPs, and runtimes, including fast system simulators, security subsystems, SoC analytics, tracer and debugger, software stacks and more. “

The V5 AndesCores inherit the compact, modular and extensible advantages from the RISC-V technology and also enjoy its fast-growing ecosystem. In addition to full compatibility to RISC-V technology by supporting its standard instructions, AndeStar V5 architecture brings Andes-extended features already proven in high-volume V3 AndesCores to be effective and beneficial to embedded applications.

Andes is a major contributor to the RISC-V open source software, ranging from GCC and LLVM compilers, libraries, debuggers, to U-Boot and the Linux kernel and its key components. In addition, Andes also plays a key role to grow the RISC-V architecture, acting as the chair of ISA P-extension (Packed DSP) Task Group and the co-chair of Fast Interrupt Task Group. Andes is committed to taking RISC-V mainstream by helping accelerate the ecosystem growth together with partners.