Read more about the article Seven Years of Uninterrupted Growth: Andes Technology Achieves Milestone Annual Revenue Exceeding NT$1 Billion

Seven Years of Uninterrupted Growth: Andes Technology Achieves Milestone Annual Revenue Exceeding NT$1 Billion

Andes Technology Is the Number One Provider of RISC-V CPU IP According to the SHD Marketing Report

 【Mar. 21, 2024-Hsinchu, Taiwan】Since its IPO in 2017, Andes Technology (TWSE:6533) has established itself as a leader in the CPU IP sector, achieving a fivefold increase in sales over the past seven years. Andes has invested capital and R&D manpower to accelerate the launch of high-end products to ensure long-term competitiveness and maintain market leadership. It is expected that a competitive product portfolio will create the next wave of revenue peaks.

(Image Source: SHD 2024 RISC-V Market Analysis)

With close monitoring of market dynamics and technology trends and decisive decision-making, Andes has strategically positioned the company to adeptly navigate challenges and seize emerging opportunities, such as bringing innovations in its proprietary AndeStar™ V3 ISA to the RISC-V based AndeStar™ V5 ISA in 2016. In 2023, even when the whole industry was still under inventory pressure, Andes surpassed a significant total shipment milestone of 14 billion Andes-Embedded™ SoCs. According to the SHD marketing report released on Jan 2024, Andes has secured an impressive 30% market share of RISC-V based chip shipping volume through its worldwide customers and is the number one provider of RISC-V CPU IP.

In 2023, the diverse product portfolio offered by Andes has resonated exceptionally well with the market and enabled its sustained growth. Andes has successfully launched the groundbreaking vector processor-AX45MPV, and the industry-revolutionizing automotive ISO 26262 fully certified core N25F-SE. More recently, Andes ventured into the application processor market with the launch of its cutting-edge out-of-order (OOO) processor AX65. AndesCore™ D23 and N225 are also released for the compact, performant, and secure applications. Besides the CPU IPs, Andes has also established a new product line, AndesAIRE™ or Andes AI Runs Everywhere, which offers a comprehensive hardware and software solution designed for edge and end-point inference.

Andes’s unwavering commitment to customer satisfaction has fostered robust relationships with its customers and fortified its market position. The addressable market segments of Andes products span a wide spectrum, encompassing AI/ML, 5G communications, FPGAs, image processing, IoT, MCU/MPU, sensors, storage, TDDI, and wireless connectivity.

Looking ahead, Andes would continue its dedication to innovations, customer satisfaction, and continual adaptation in the dynamic CPU IP licensing market. Below are a set of key drivers underpinning Andes’ growth:

Expansion of AI and HPC Applications: The ongoing surge in demand for AI and High-Performance Computing (HPC) applications, coupled with the requirements for specialized SoC, serves as one of the primary catalysts for Andes. Offering processors enhanced with ACE™ (Andes Automated Custom Extension) to meet the stringent requirements of AI and HPC workloads has significantly contributed to Andes’ market growth.

Increasing Demands for Automotive-Grade (ISO 262626) SoC: As the automotive industry continues to advance, there is a rising need for Automotive-Grade SoCs compliant with the ISO 262626 standard. Andes has seized this trend and is actively catering to the increasing demands for automotive-grade solutions. By offering processors designed to meet the stringent safety and reliability requirements of the automotive sector, Andes is well-positioned to capitalize on this growing market segment, further enhancing its success and market penetration.

Maturity of the RISC-V Ecosystem: By actively participating in the RISC-V International and community with the highest RVI membership and Summit sponsorship, Andes contributes to the RISC-V ecosystem’s fast expansion. Through this effort, Andes remains at the forefront of RISC-V development, fostering a positive cycle benefiting both the company and the ecosystem.

Rise of Multi-Core Heterogeneous SoC: The growing complexity of modern applications, spanning various domains like AIoT, edge computing, and data centers, has led to the rise in multi-core heterogeneous System-on-Chips (SoCs). Andes’ strategic focus on developing a diverse product portfolio aligns seamlessly with the demands of multi-core heterogeneous SoCs. These processors offer the performance and flexibility needed to address the contemporary applications’ requirements.

“Andes Technology’s journey of consistent growth over the past seven years is a testimony to our unwavering determination of staying ahead of industry trends and commitment to customers,” said Frankwell Lin, the Chairman, and CEO of Andes Technology. “We remain dedicated to shaping the future of the CPU IP licensing market with cutting-edge solutions.”

“As Andes charts our roadmap for the future, with ‘Driving Innovations’ as our motto, on one hand, we are developing high-end products that push the boundaries of performance,” remarked Dr. Charlie Su, the CTO and President. “On the other hand, we continue to deliver strong compact processors for power-efficiency and security. Aligning our expertise with the evolving needs of this dynamic industry, our talented team and effective collaboration with customers will continue to drive us forward, shaping the future of high-performance and high-efficiency computing, complying to strict safety demands in automotive SoC, and addressing the ever-emerging AI requirements.”

 

About ANDES RISC-V CON
ANDES RISC- V CON is the annual RISC-V technology forum hosted by Andes Technology and sponsored by partners. In 2024, the San Jose session will be held in Doubletree by Hilton Hotel on June 11. The 2024 theme is “Deep Dive into Automotive/AI/Application Processing and Security Trends.” It will introduce the flexible RISC-V processors that changes the face of emerging computing and share how Andes assists the RISC-V ecosystem in implementing diversified applications of innovative technologies. Four popular application areas will be focused on: AI/ML, automotive electronics, application processing and security. Many ecosystem partners are invited to give talks and on-site demonstrations. For free registration, please see the official website of Andes RISC-V CON https://www.andestech.com/Andes_RISC-V_CON_2024_US/

 

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety, and/or multicore capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Facebook, X, Bilibili and YouTube! 

Continue ReadingSeven Years of Uninterrupted Growth: Andes Technology Achieves Milestone Annual Revenue Exceeding NT$1 Billion

Andes晶心科技推出全新产品线AndesAIRE™ 对边缘与终端设备人工智能推理提供极高效率解决方案

【台湾新竹】— 2023 年 5 月 15日 —32/64位、高效能低功耗的RISC-V处理器核心领导供货商暨RISC-V国际协会创始首席会员Andes晶心科技今日宣布全新产品线 AndesAIRE™ 或 Andes AI Runs Everywhere 正式上市，该解决方案为边缘及终端设备人工智能推理提供极高的计算效率。AndesAIRE™ 包含首代人工智能和机器学习（AI/ML）硬件加速器IP AndesAIRE™ AnDLA™ I350（Andes Deep Learning Accelerator），以及神经网络软件开发工具包 AndesAIRE™ NN SDK。

随着人工智能和机器学习（AI/ML）应用的爆炸性成长，高效能与高效率深度学习解决方案的需求不断增加。在此需求下，由于边缘和终端运作环境严格的功耗限制，使得仅仅依赖CPU架构变得困难。针对这样特别的挑战，Andes晶心科技推出AndesAIRE™ AnDLA™ I350，提供行业领先的高效率、低功耗和小面积，非常适合广泛应用于边缘推理应用，包括智能物联网设备和智能相机，到智能家电和机器人等应用。

AndesAIRE™ AnDLA™ I350 建立在Andes晶心科技过去18年来CPU 技术中累积的计算加速经验，并提供了一个高效能的AI/ML加速平台。该解决方案支持主流的深度学习框架，例如 TensorFlow Lite、PyTorch 和 ONNX，以及在 int8 数据类型中执行多种神经网络算子，例如convolution, fully-connect, element-wise, activation, pooling, channel padding, upsample, concatenation等。此外，AnDLA™ I350 内部设备直接内存访问（DMA）和本地内存（local memory），以发挥硬件计算引擎的最佳计算能力。而operator fusion技术也是其特色之一，能更有效地执行常见的计算序列。AnDLA™ I350主要可配置参数包括从 32 到 4096 MAC 计算能力， 16KB 到 4MB 的SRAM 大小，为广泛的应用提供64 GOPS 到 8 TOPS（在1 GHz下）灵活计算能力。

AndesAIRE™ NN SDK 是一套全面的软件开发工具包，可用于端到端（end-to-end）的开发与部署。它包括以下部分：

  • AndesAIRE™ NNPilot™: 神经网络优化工具套件
  • AndesAIRE™ TFLM for AnDLA™：专为 AnDLA™ 优化的TensorFlow Lite for Microcontrollers框架
  • AnDLA™ driver and runtime
  • NNPilot™ 可自动分析输入的神经网络模型，进行模型剪枝（pruning）和模型量化（quantization），根据硬件配置产生 AnDLA™ 可执行文件，并于 TFLM 框架下进行模型推论。
  • NNPilot™ 还会生成样本 C 代码，在主机的裸机环境中调用 AnDLA™ 驱动程序。

为因应不断进展与快速发展的人工智能技术，Andes晶心科技致力于开发可扩展的人工智能子系统，能完美结合AndesAIRE™ AnDLA™、AndesCore® RISC-V CPU和Andes Custom Extension™ （ACE）。在此子系统中，人工智能工作负载中大部分结构化与计算耗时的部分将有效率地在 AnDLA™ 中计算，而如非线性函数等较不结构化的计算可以通过RISC-V DSP/SIMD或Vector指令扩展的处理器中进行计算。其中ACE 是 CPU 和 AnDLA™ 之间进行高效数据传输的重要关键，能减少海量存储器带宽和功耗，并同时大幅提高硬件利用率。ACE 还可以针对特定领域计算设计客制化指令，例如数据的前与后处理，来进一步提升处理效能。除了硬件IP 的可扩展性外，Andes晶心科技不断投入开发软件 AndesAIRE™ NN SDK 和 AndesAIRE™ NN Library，使得已量产的SoCs可以因应未来人工智能算法的演进。自 2021 年以来，Andes晶心科技每年于其计算函式库中增加了超过一百个函数，并且将持续优化和扩展新功能到 NN SDK 和 NN library 中。

「Andes晶心科技非常高兴推出我们人工智能和机器学习（AI/ML）解决方案的新产品系列，包括AndesAIRE™ AnDLA™ I350和AndesAIRE™ NN SDK。这是一款包含杰出效能的硬件以及专为边缘和端点人工智能推理设计的端到端软件解决方案，」Andes晶心科技总经理暨技术长苏泓萌博士表示。「透过AndesAIRE™，我们赋予开发人员和创新者打造高扩展性和面向未来的AI/ML的芯片和应用。」

「AndesAIRE™ 产品线展现了我们对于AI/ML的市场愿景。」 Andes晶心科技市场处资深技术经理王庭昭表示，「透过融合 RISC-V 处理器、AnDLA™ 和 ACE 的优势而成的一个人工智能子系统，可充分平衡效能、功耗和面积，提供客户极具竞争力的解决方案。不仅如此，RISC-V 处理器和 NN 软件栈确保了弹性，而丰富的扩展性也让客户为其AI/ML特定应用建立出独特的价值。」 

AndesAIRE™ AnDLA™ I350和AndesAIRE™ NN SDK现在正开放早鸟授权项目。欲获得更多信息，请访问Andes晶心科技网站：http://www.andestech.com/en/products-solutions/andesaire-ai/。

【关于Andes RISC-V CON】

Andes晶心科技年度RISC-V技术论坛，2023年场次包括5/16于新竹国宾饭店，5/23于上海博雅酒店，5/25于北京丽亭华苑酒店等地线下举办。本年以“RISC-V重塑世界， 翻转AI、车用电子、ANDROID战略布局”为题。介绍改变新兴运算面貌的RISC-V灵活优势，并分享晶心协助RISC-V生态系实现多元应用的创新技术。本次活动将聚焦三个热门应用领域，包括人工智能、车规电子以及RISC-V新踏入的Android领域，并邀请到众多RISC-V生态伙伴进行专题演讲及现场展示。免费报名及议程请参阅活动官网:
5/16(二)新竹场 https://www.andestech.com/Andes_RISC-V_CON_2023_TW/。
5/23(二)上海场、5/25(四)北京场 https://www.andestech.com/Andes_RISC-V_CON_2023_CN/。

Continue ReadingAndes晶心科技推出全新产品线AndesAIRE™ 对边缘与终端设备人工智能推理提供极高效率解决方案

Andes RISC-V CON聚焦HPC、車用、AIoT三大创芯应用领域
探讨RISC-V多元解决方案

◎8月11日Andes RISC-V CON 立即在线免费报名

 根据Counterpoint Research 2021调查报告指出，随着半导体解决方案中所需之IP技术要求更多元，纯IP供货商之市场将以年复合成长率11%的持续扩大，于2025年达到86亿美元的市场规模。而RISC-V因其开源优势、极佳的功耗比、高安全性等因素，在IP授权市场中具有强劲成长之优势，预计在2025年将于IoT应用、工业应用、车用等三大产业中，成长至分别占28%、12%、10%的市场占有率，成为应用的关键领域。在日前Embedded World活动上，RISC-V International CEO Calista Redmond也透露: RISC-V架构芯片出货量已突破百亿颗，2025年RISC-V架构芯片有望突破800亿颗，这些数据都一再说明RISC-V 这个架构已占有相当规模的市场基础。

Andes晶心科技已推出多款RISC-V处理器解决方案，将于8月11日，以「引领RISC-V运算大时代‧驾驭未来多元芯应用」为主题，介绍改变新兴运算面貌的RISC-V灵活优势，聚焦于高速运算(HPC)、车用电子(Automotive)、AIoT等三大领域介绍Andes 解决方案，并分享晶心协助RISC-V生态系实现多元应用的创新技术，与会的生态系伙伴包括Renesas 瑞萨电子、HPMicro上海先楫半导体科技、IAR System、Menta、Siemens西门子等RISC-V 生态伙伴，欢迎免费在线报名。

本次Andes RISC-V CON开场将由晶心科技董事长暨RISC-V国际协会董事林志明以 「RISC-V蔚为运算主流」为题，放眼国际，分析RISC-V成为业界主流标准的原因、规格批准(ratification)的趋势及影响的应用领域。晶心科技总经理暨技术长苏泓萌博士则将主持研讨会的Q&A，进一步解说关于RISC-V的最新技术发展动态。

除此之外，Andes RISC-V CON将剖析全方位的RISC-V高效运算解决方案，适合数据中心、高效能运算(HPC)以及AI Cloud端等级应用开发，同时探讨RISC-V如何实现车用芯片对于信息安全、功能安全与可靠度的技术要求，另解析发展快速的AIoT与TinyML应用，介绍契合AI运算需求并兼具性能和效率的RISC-V解决方案。

此外，本次研讨会还邀请到众多RISC-V生态伙伴进行专题演讲，其中MCU龙头瑞萨电子将分享采用RISC-V的微处理器解决方案；先楫半导体将介绍其国产RISC-V 高性能MCU先楫HPM6000系列及如何应用于中高端工业市场；编译程序软件大厂IAR Systems将说明如何透过IAR系统助力RISC-V 开发；eFPGA领导厂商Menta则将介绍如何结合RISC-V让客户自定指令(ACE)在eFPGA中更容易重新编置，为开发和差异化保留发展空间；而工业应用大厂西门子(Siemens EDA)也将说明一种基于硬件来达到侦测威胁，以达到网络安全的设计、其车辆开放系统架构部门(Siemens AUTOSAR)，也将以其车用电子为主题，分享最新技术。Andes将联合RISC-V 生态系伙伴一同带来最新RISC-V应用与技术趋势。

立即免费在线报名，全程参与还可以抽中开发板等奖品带回家！

◎晶心Andes受邀专题演讲及活动摊位

 欢迎加入我们的微信公众号(AndesTech)并到摊位领取赠品

08/24-08/26 RISC-V Summit China@online : Keynote及专题演讲

  • The Atomicity and Consistency Issues When Programming IOPMP
  • TVM AutoScheduler on Andes Bare-Metal Platform with Vector Extension
  • Supporting RISC-V SMP and AMP in the Zephyr LTS Release
  • The Out-of-Box MLPerf-Tiny Benchmarks on Andes RISC-V Platform

11/09-11/10 ICCAD@广州: 专题演讲：RISC-V 车用电子解决方案

Early Dec TSMC OIP China: 专题演讲

◎晶心科技新闻集锦

AndeSight™ v5.1包括晶心先进的RISC-V超纯量多核A(X)45MP和RISC-V向量处理器NX27V，适合用于异构RISC-V多处理器。AndeSight™ v5.1支持具有SMP及AMP的操作系统，且提供充足的RVP和RVV工具链的支持，使开发人员只须专注于应用程序开发。总结来说，该解决方案能协助并简化嵌入式系统的开发，并为客户提供多功能的整合环境。

物联网量子驱动网络安全专家Crypto Quantique加入晶心科技AndeSentry™ 安全框架，提供全面的安全解决方案，以抵御网络及物理性等各种机制的攻击。双方合作涵盖Crypto Quantique的量子驱动半导体信任根IP、QDID、以及从芯片端到云端的物联网装置安全管理平台，携手为客户带来工业级网络安全解决方案，并协助客户防范网络攻击以取得竞争优势。

物联网安全公司领导者 ZAYA 的安全操作系统与晶心AndesCore™ RISC-V 处理器成功整合，以提供可认证的 TEE (可信任运行环境安全系统) 安全系统。藉由 AndeSentry™ 安全合作框架，芯片制造商可以完成开发内嵌AndesCore™ 的安全设备。双方合作的解决方案为RISC-V 生态系统提供丰富的安全解决套装方案，有助于加速AIoT设备、连网设备和车用设备等开发。

源自开源技术，并提供支持AI功能之特定领域应用的FPGA 供货商 Rapid Silicon已采用带有DSP/SIMD扩充指令集的AndesCore™ D45以及客制化扩充功能架构 (ACE)。这项合作结果将广泛地应用在电信、汽车、数据处理和工业计算机的垂直市场，使客户加速开发SoC并缩短产品上市时间。

晶心科技与嵌入式开发全球领导者IAR Systems一同合作，结合各自专业知识为车载应用提供一流的性能。双方共同宣布来自欧洲及亚洲的IC领导厂商已采用晶心科技车用CPU核心及IAR Systems RISC-V功能安全认证开发工具。此开发工具所采用之晶心科技CPU核心N25F，能预防系统性失效，以达到汽车功能安全(FuSa)的目的。此合作结合两家公司之专业知识为其客户的车载应用提供第一流的性能及安全性。

随着车用市场的发展，功能安全和可靠解决方案的国际标准也日益重要。晶心科技宣布通过ISO 26262验证，证明系统性的流程开发能力已达到汽车安全完整性等级的最高等级ASIL D，符合车用功能安全处理器核心开发标准。根据正式记录，在2020年12月晶心成为第一家同时获得硬件(ISO 26262-5)和软件(ISO 26262-6)流程验证的RISC-V处理器IP供货商。

Continue ReadingAndes RISC-V CON聚焦HPC、車用、AIoT三大创芯应用领域
探讨RISC-V多元解决方案

上海先楫半导体发布微控制器HPM6000系列 采用晶心AndesCore® 双D45内核
强大算力加速智能工业、智能家电、边缘计算及物联网等应用

目前全球性能最强的实时RISC-V微控制器HPM6000系列，主频高达 800MHz，创下超过9000 CoreMark™ 和4500 DMIPS性能的新记录

【中国上海】 2021年11月24日，高性能嵌入式解决方案领导厂商上海先楫半导体(HPMicro Semiconductor Co., LTD.)与32/64位RISC-V嵌入式处理器核心领导供货商晶心科技(Andes Technology, TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099)，今日共同发布目前全球性能最强的实时RISC-V微控制器HPM6000系列。该系列旗舰产品HPM6750采用双Andes D45 RISC-V内核，配置创新总线架构、高效的L1缓存和本地存储器，创下超过9000 CoreMark™和4500 DMIPS性能的新记录，主频高达 800MHz，为边缘计算等应用提供强大的算力。

HPM6000 MCU全系列产品，包括多核的HPM6750、单核的HPM6450，及入门级的HPM6120版本，都具有双精度浮点运算及强大的DSP扩展指令，内置2MB SRAM，以及丰富的多媒体功能、马达控制模块、通讯接口及安全加密。HPM6000系列具备高效能、低功耗、高安全的特点，可广泛应用于智能工业、智能家电、金融终端支付系统、边缘计算及物联网等热门应用。

AndesCore® D45是晶心科技RISC-V家族45系列成员之一，采用顺序执行的8级双发射超纯量技术，具有优化的存储流水线设计以及进阶分支预测功能，同时支持符合IEEE754的单/双精度浮点运算单元（FPU）及RISC-V P扩展指令 (DSP/SIMD)。45系列内核也具有区域内存(local memory)支持的储存子系统，以及可配置的指令及数据高速缓存，对支持海量存储器的SoC例如HPM6000系列，可进一步提升其软件效能。D45核心非常适合用于对响应时间和实时准确性有特别要求的嵌入式应用产品。

「上海先楫的HPM6000系列产品具备高速算力和实时控制功能，将提供全球高阶MCU市场更灵活及高效的选择。」晶心科总经理暨首席技术官苏泓萌博士表示：「藉由晶心科技的D45并配合支持AndeStar™ V5之Segger Embedded Studio®开发工具，客户得以设计出更高效能、且程序代码更精简的软件。上海先楫领先同业，推出内嵌高效能RISC-V核心之MCU安全解决方案，展示团队的超高的效率及卓越的研发能力。」

「Andes D45是唯一达到先楫半导体超高速实时运算要求的RISC-V处理器内核，在某些测试环境下，性能甚至超过其他竞争者50%！而晶心在产品导入的实时技术支持，协助我们成功并快速地完成HPM6000系列的Tape out，双方团队完美地进行了一次紧密高效的合作。」先楫半导体首席执行官曾劲涛表示：「先楫半导体为开发者提供完备的生态系统，包括一个基于VS CODE框架的免费集成开发环境HPM Studio，以及PC端图形接口的SoC资源分配工具。先楫半导体还将推出基于BSD许可的SDK，其中包含底层驱动程序，中间件和RTOS。所有官方软件产品都将开源，并配以高性价比的评估报告，先楫半导体将会与RISC-V社群的伙伴合作，为打造更好的RISC-V软件生态作出贡献。 

订购/样片信息
HPM6750，HPM6450系列产品将于2021年12月底开始提供样片和评估板，如需订购可邮件至 info@hpmicro.com，更多信息敬请访问www.hpmicro.com

关于先楫半导体 (HPMicro Semiconductor)
先楫半导体是一家致力于高性能嵌入式解决方案的半导体公司，成立于2020年6月，总部坐落在上海张江，在天津和武汉设有子公司。先楫半导体的产品覆盖微控制器、微处理器和周边芯片，以及配套的开发工具和生态系统，先楫半导体具备成熟的研团队，各研发关键职能（构架，模拟，SOC，数字，IP，DFT，后端等）均由资深工程师负责。公司现有研发队伍绝大部分拥有硕士以上学历，包括博士数名。

2021年 10月，先楫半导体成功完成近亿元PRE-A轮融资，由中芯聚源领投，东方电子关联基金和创徒投资跟投。

先楫半导体将与世界知名晶圆厂、封装测试厂及其它战略合作伙伴一起，共同推进互联网，工业自动化，消费电子等半导体领域的技术创新。更多关于先楫半导体的信息，请访问www.hpmicro.com。

关于晶心科技 (Andes Technology)
晶心科技股份有限公司于2005年成立于新竹科学园区，2017年于台湾证交所上市(TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099)。晶心是RISC-V国际协会的创始首席会员，也是第一家采用RISC-V作为其第五代架构AndeStar™基础的主流CPU供货商。为满足当今电子设备的苛刻要求，晶心提供可配置性高的32/64位高效CPU核心，包含DSP，FPU，Vector，超纯量(Superscalar)及多核心系列，可应用于各式SoC与应用场景。晶心并提供功能齐全的整合开发环境和全面的软/硬件解决方案，可帮助客户在短时间内创新其SoC设计。在2020年，Andes-Embedded™ SoC的年出货量突破20亿颗；而截至2021年第三季，嵌入AndesCore® 的SoC累积总出货量已达90亿颗。
更多关于晶心的信息，请访问晶心官网https://www.andestech.com。追踪晶心最新消息：LinkedIn、Facebook、Weibo、Twitter、Bilibili以及YouTube。

Continue Reading上海先楫半导体发布微控制器HPM6000系列 采用晶心AndesCore® 双D45内核
强大算力加速智能工业、智能家电、边缘计算及物联网等应用

耐能智能边缘运算芯片KL530进入量产 晶心RISC-V D25F处理器协助提升算力
共同实践“AI 无处不在”的愿景

【美国加州圣地亚哥】 2021年11月4日，边缘运算(Edge AI)解决方案领导厂商耐能智慧(Kneron)与32/64位RISC-V嵌入式处理器核领导供货商晶心科技(TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099)，今日共同宣布耐能智慧下世代AI智能边缘运算芯片KL530已正式量产。KL530采用晶心的D25F处理器，它包含高效的流水线、强大的Packed-SIMD DSP 扩展指令及符合 IEEE754 的高性能单/双精度浮点RVFD扩充指令集。

KL530是耐能智能的最新型异构AI芯片，采用全新的NPU架构，它是业界中第一个支持INT4精度和Transformer运算的产品。相比其它芯片，KL530具有更高的运算效率及更低功耗。这款AI 芯片内嵌RISC-V CPU并具备强大的图像处理能力和丰富的接口，能进一步促进边缘智能芯片在ADAS、AIoT等方面的应用。KL530算力达1 TOPS INT 4，在同等硬件配置下INT 8的处理效率提升高达70%，其可重构NPU设计搭配RISC-V D25F核的高效能运算，可支持CNN、Transformer、RNN Hybrid等多种AI模型，还有智能ISP可基于AI优化图像质量、强力Codec实现高效率多媒体压缩，并且冷启动时间低于500ms，平均功耗低于500mW。

D25F CPU 是 AndesCore™ 25 系列中被广泛使用的核之一，它支持 RISC-V P扩充指令集标准草案(RISC-V P-extension ISA draft)，可在一条指令中高效地同时处理多笔数据。晶心是P扩展指令集的原始架构者，并在RISC-V 国际协会的任务组主导其规格制订。D25F 提供完整的开发工具，包括根据向量数据格式自动生成 SIMD 指令的编译程序、优化的DSP函数库、神经网络函数库和近精确周期仿真器。D25F在常用的机器学习算法上能提供近9倍的加速，包括 Tensorflow 关键词识别、CIFAR10 图形分类和 P-net 对象侦测等。

“耐能拥有独特的可重组式架构，可以轻松融入不同的卷积神经网络(CNN)而不需对设计需求妥协，从而无缝、精确地应用于各种 AI 模型。”耐能智慧创始人兼首席执行官刘峻诚表示。“晶心D25F CPU 核和其强大的 DSP 指令及其软件开发框架使耐能可以在不牺牲最佳功耗表现的条件下，最大限度地探索其领先同行的AI算法性能。这对我们的客户至关紧要。我们很高兴能与专注RISC-V领域并取得领先地位的计算专家晶心科技合作。凭借晶心RISC-V核和DSP解决方案，耐能能够在很短的时间内，顺利开发出这款高端解决方案，我们非常自豪现在 KL530 已投入量产并开始服务我们的客户。”

“我们很高兴耐能智能在经过一系列综合评估后，选择 D25F为KL530的CPU核，”晶心科技首席执行官暨RISC-V国际协会董事林志明表示：“D25F在产品特点、效能、核面积、功耗等各项关键指标都表现优异。耐能领先同业，提供内嵌RISC-V核的边缘AI SoC解决方案，并快速推出KL530进入量产，展示了团队的超高的效率。耐能的强大竞争力令人震惊。感谢耐能与晶心的密切合作，我们共同完成了极具竞争力的解决方案，并将加速人工智能应用进入各式产品中。”

关于Kneron KL530 在线发表会

Kneron KL530在线产品发表会将于美西时间11月4日上午10:00-11:30 (PDT)举行，包含全球半导体联盟(GAS) CEO Jodi Shelton、华邦科技陈沛铭总经理、YouTube创办人陈士骏等人均受邀演讲，发表他们对于下一代边缘运算Edge AI的看法，报名信息 https://www.kneron.com/en/event-registration/ab29527e

关于耐能智慧（Kneron）

耐能智慧（Kneron）于 2015 年创立于美国圣地亚哥，是终端人工智能解决方案的领导厂商，提供软硬件整合的解决方案，包括终端装置专用的神经网络处理器以及各种影像识别软件。耐能智能将人工智能技术深入扩展到终端设备、硬件AI芯片与软件AI模型等，满足大从自动驾驶、智能冰箱，小至门铃或各式AIoT产品的需求。Kneron所提供的智能设备具备安全性、超低功耗与低成本三大优势，致力实现“AI无处不在”的愿景。Kneron 目前在圣地亚哥、台北、深圳、珠海已成立办公室，并拥有全球客户和合作伙伴。

Kneron 于 2017 年 11 月完成 A 轮融资，投资者包含阿里巴巴创业者基金（Alibaba Entrepreneurs Fund）、中华开发资本国际（CDIB）、奇景光电（Himax Technologies, Inc.）、高通（Qualcomm）、中科创达（Thundersoft）、红杉资本（Sequoia Capital）的子基金Cloudatlas以及创业邦。2018 年 5 月与 2020 年 1 月，耐能分别完成由李嘉诚旗下的维港投资（Horizons Ventures）领投的 A1 轮与 A2 轮融资。截至目前为止，Kneron 获得的融资金额累计已超过一亿美元。更多关于耐能智能的信息，请参阅 https://www.kneron.com/en/

关于晶心科技 (Andes Technology)
晶心科技股份有限公司于2005年成立于新竹科学园区，2017年于台湾证交所上市(TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099)。晶心是RISC-V国际协会的创始首席会员，也是第一家采用RISC-V作为其第五代架构AndeStar™基础的主流CPU供货商。为了满足当今电子设备的苛刻要求，晶心提供了可配置性高的32/64位高效CPU核，包含DSP，FPU，Vector，超纯量(Superscalar)及多核系列，可应用于各式SoC与应用场景。晶心并提供功能齐全的整合开发环境和全面的软/硬件解决方案，可帮助客户在短时间内创新其SoC设计。在2020年，Andes-Embedded™ SoC的年出货量突破20亿颗，而截至2020年底，嵌入AndesCore™的SoC累积总出货量已超过70亿颗。
更多关于晶心的信息，请参阅晶心官网https://www.andestech.com。追踪晶心最新消息：LinkedIn、Facebook、Weibo、Twitter、Bilibili以及YouTube。

Continue Reading耐能智能边缘运算芯片KL530进入量产 晶心RISC-V D25F处理器协助提升算力
共同实践“AI 无处不在”的愿景

Imperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test Suites

Imperas simulation technology and reference model available for free, including test suites for basic processor hardware verification and compliance testing

Imperas press release on SIMD/DSP RISC-V P Extension

 

Oxford, United Kingdom, July 19th, 2021 — Imperas Software Ltd., the leader in RISC-V processor verification technology, announces the latest updates to riscvOVPsimPlus with support for the near ratified P extension and architectural validation test suites. The P (or Packed SIMD/DSP) extension is a significant addition to the flexibility of the modular RISC-V ISA (Instruction Set Architecture); it supports real-time data processing applications as part of the main processor pipeline without the need for the associated inefficiencies of a co-processor. For processor hardware verification, a basic test suite helps ensure implementations have a basic software level compatibility to the new P extension as a reference to the developers’ interpretation of the written specification.

riscvOVPsimPlus is a popular free ISS (Instruction Set Simulator) that is an envelope model that can be configured to cover all of the ratified RISC-V specifications and standard extensions. Also included are several Architectural Validation Test Suites, which form a basic test plan for software level compatibility within the specification definitions. The Imperas models are available as open- source and licensed under the Apache 2.0 flexible open-source license. All models, virtual platforms and example models are provided to the community via the Open Virtual Platforms website www.OVPworld.org. The Imperas commercial simulation technology and products are based on the freely available open-standard public OVP APIs.

The Imperas RISC-V architectural validation test suites are collections of tests focused on specific ISA extensions that provide basic testing of instruction execution and usage of the full range of operands with a set of representative data values. They are not a substitute for full detailed tests suites for design verification but provide detailed coverage reports of the different parts of the architectural specification tested. The currently released test suites available free on the OVP website now include P-SIMD/DSP, K-crypto, V-vector, B-bitmanip, F, D, I, M, and C.

“Flexibility within a framework of compatibility is the essential foundation of the RISC-V ISA,” said Chuanhua Chang, Andes Technology Corporation, Chair of RISC-V International P Extension Task Group. “The RISC-V P extension defines a rich set of integer SIMD/DSP instructions operating on existing integer registers to support complex data processing within the constraints of real-time applications. However, the hardware specification is just the start – adoption and success depend on the software ecosystem, which is supported with the reference models and test suites from Imperas.”

“By combining SIMD/DSP functionality within the RISC-V ISA offers the ideal balance for performance, flexibility and efficiency,” said Wei Wu, PLCT Lab, ISCAS, Vice-Chair of RISC-V International P Extension Task Group. “The Imperas RISC-V reference model provides the ideal starting point to explore and develop software algorithms based on the new RISC-V P extension.”

“The Imperas simulation technology and RISC-V reference models are in active use in some of the most complex RISC-V verification projects,” said Simon Davidmann, CEO at Imperas Software Ltd. “RISC-V is changing the design process as new design exploration can start without many of the traditional barriers. The adoption of riscvOVPsimPlus with the new RISC-V P extension support helps provide clarification of the specification boundary as a useful guideline for innovation in new processor designs.”

 

About RISC-V Processor Verification IP

The free riscvOVPsimPlus package including the test suites and functional coverage analysis are now available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.The riscvOVPsimPlus solution is an entry ramp for development and verification and includes a proprietary freeware license from Imperas, which covers free commercial use as well as academic use. The simulator package also includes a complete open-source model licensed under the Apache 2.0 license.

The RISC-V processor Verification IP, example test benches and any customer-specific test suites are Imperas commercial solutions. Imperas also provides solutions for developers of more advanced RISC-V designs, who need multicore, or custom instruction support and advanced verification techniques. Imperas also offers a rich library of models for virtual platforms as used in early software development and hardware verification, including methodologies around continuous integration and regression using ‘virtual’ test farms, plus support for hybrid verification platforms with hardware emulators provided by Cadence Palladium, Siemens EDA Veloce, and Synopsys Zebu.

The Imperas simulation technology and reference models support the full spectrum of RISC-V processor verification requirements from a basic functional test, routine specification compliance, coverage driven verification, right through to the latest step-and-compare flows. The step-and- compare methods used for complex designs cover both asynchronous events and also, when integrated into a UVM SystemVerilog test bench, provide a seamless environment for efficient debug and analysis. To learn more about the options for RISC-V verification, visit www.imperas.com/riscv.

About Imperas

Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multicore systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

 

Continue ReadingImperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test Suites

Andes certifies Imperas RISC-V Reference Models for the new RISC-V P (SIMD/DSP) extension

Imperas simulation technology and RISC-V reference models updated to cover the RISC-V P Extension for SoC architecture exploration and early software development

Andes Certifies Imperas RISC-V Reference Models For The New RISC-V P (SIMD/DSP) Extension

Oxford, United Kingdom, July 12th, 2021 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced that Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V CPU cores and a Founding Premier member of the RISC-V International Association, has certified the Imperas reference models for the complete range of Andes IP cores with the new RISC-V P extension. Developers can now use the Imperas reference models to evaluate multicore design configuration options for SoC architecture exploration.

The open standard RISC-V ISA (Instruction Set Architecture) has a modular structure based on multiple independent extensions that offer dedicated and enhanced functionality to optimize a processor for the target application. The new SIMD/DSP extension, designated as ‘P’ in the specification description, supports efficient data processing applications and real-time requirements. The RISC-V International P Extension Task Group is in the final stages of submitting the specification to the official ratification process, which is expected to be completed within H2 2021.

The Imperas simulation technology enables fast and accurate virtual platforms that are central to modern SoC design and embedded software development. Working with lead customers, the Imperas models of the Andes cores have already been used for commercial projects, which are now implemented in silicon.

Optimizing a multicore design is one of the most challenging design tasks. Multiple independent processing units interacting with each other plus shared peripherals together with real-time processing tasks supporting a mix of OS/RTOS running firmware and application software. SoC architecture exploration allows a full evaluation of software running before the final decision and configuration of the hardware options. These virtual prototypes also support early software development, often many months before silicon prototypes are available. For final software testing, a virtual platform allows the actual binary code to be verified with access and visibility not available in real hardware or without compromising the software under test with additional test code.

“RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations,” said Dr. Charlie Su, President and CTO at Andes Technology Corp. “The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.”

“Embedded development depends on the optimized balance between hardware resources and software applications,” said Simon Davidmann, CEO at Imperas Software Ltd. “With the Imperas golden reference models, developers can explore full software development for all the Andes cores, including the new RISC-V P extension and Andes ACE custom instructions.”


About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020, and the cumulative volume has reached 7 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook and YouTube!

About Imperas
Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multicore systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

Continue ReadingAndes certifies Imperas RISC-V Reference Models for the new RISC-V P (SIMD/DSP) extension