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Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel

RISC-V: Shaping the Future of AI/ML, Application Processors, Automotive, and Security

San Jose, CA — Jun 6, 2024 — Andes Technology (TWSE: 6533), the leading vendor in high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, unveils its agenda of the annual ANDES RISC-V CON on June 11th at the San Jose Airport DoubleTree Hotel. This year’s theme, “ANDES RISC-V CON: Deep Dive into Automotive/AI/Application Processors and Security Trends,” promises an exhilarating journey into the RISC-V advancements. With over 300 registered attendees, this conference is set to be an industry luminary event, bringing together top-tier experts, researchers, and industry leaders for riveting discussions and groundbreaking insights.

The ANDES RISC-V CON boasts an exceptional lineup of presentations and two dynamic panels featuring key players in the RISC-V ecosystem. The AI panel, moderated by Dylan Patel, Chief Analyst at SemiAnalysis, includes Charlie Cheng from Andes Technology, Chris Walker from Untether AI, Jim Keller from Tenstorrent, and Raja Koduri from Mihira AI. This session will dive deep into “How Open-Source is Transforming AI and Hardware”. Another highlight is the Application Processing panel, moderated by Mark Himelstein, and with panelists consisting of Barna Ibrahim from RISE, Charlie Su from Andes Technology, Lars Bergstrom from Google, and Sandro Pinto from OSYX Technologies. This session will dive deep into how RISC-V eco-system aims at helping RISC-V processor to be used as application processor in a rich OS system, including Android and the others.

The event kicks off at 9:30 AM with a welcome address from Andes Technology’s Chairman and CEO, Frankwell Lin about the RISC-V market outlook, followed with a keynote by Dr. Charlie Su, President & CTO of Andes Technology, titled “Unlocking RISC-V’s Potential in Intelligent Application Processing.” From application processors to AI/ML accelerators, Dr. Su will first give an update on market adoption for RISC-V and show a couple examples of large-scale AI/ML SoCs adopting Andes AI/ML solutions. He will also explore the high-end processor usage scenarios. Marc Evans, Director of Business Development & Marketing at Andes, will discuss Andes’ automotive and security solutions. 

The exhibition will display a plethora of exciting RISC-V technologies, including the Andes Qilai testchip, a high-performance SoC with a quad-core RISC-V AX45MP cluster and an NX27V vector processor, designed to accelerate the development and porting of large RISC-V applications. Additionally, there will be an automotive-grade CMOS image sensor demo using the ISO 26262 fully-compliant AndesCore™ N25F-SE by MetaSilicon. Other demos featuring Andes RISC-V cores include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; an AI development kit with a camera module from Canaan; the IT9836 TDDI demo board from ITE; the PC802SCB 5G small cell reference design from Picocom; and a Bluetooth development kit from Telink.

Additionally, renowned companies like Green Hills, IAR, Lauterbach, Piece Makers, RAIN AI, Siemens EDA, Synopsys (Imperas), and TetraMem will have speeches and booths. Alchip, Arteris, Menta, Rambus, RISE, RISC-V International, S2C, Sapeon, SHD, Signature IP, and Sondrel will have booths to engage and interact with attendees. 

ANDES RISC-V CON is the ultimate platform for RISC-V designers and developers to engage in meaningful dialogues with global experts. The conference will offer a stimulating and delightful experience, complete with a delicious lunch buffet and a relaxing evening reception. Stay until the end for a chance to win fabulous prizes including iPad in the Lucky Draw!

Best of all, this incredible event is free to attend! Don’t miss out on this extraordinary opportunity to be part of the RISC-V revolution. Register now and join the event for a day of innovation, inspiration, and networking!

👉 Register here: https://www.andestech.com/Andes_RISC-V_CON_2024_US/

 

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedInTwitterBilibili and YouTube! ! 

 

Continue ReadingAndes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel

Rain AI Unveils Andes Technology as Its RISC-V Partner

Rain AI Licenses Andes AX45MPV and Taps Andes Custom Computing BU to Accelerate Its Launch of Groundbreaking Compute-In-Memory (CIM) Generative AI Solutions

San Francisco, CA, June 03, 2024 – Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announces that Rain AI, a pioneer in compute-in-memory (CIM) technology, licensed Andes’ AX45MPV RISC-V vector processor. Rain AI designs novel accelerator solutions, and the two companies are collaborating to accelerate Rain AI’s product roadmap.

As the world economy embraces generative AI to deliver unprecedented benefits to consumers and business alike, energy consumption stands as a significant hurdle regardless of the deployment points, be it the cloud, edge, and especially the smallest sensors. CIM represents the most promising solution to lower the energy footprint by as much as 50X. By performing computations directly in the memory bit-cells, CIM can dramatically reduce the energy required for matrix operations commonly found in machine learning.

However, CIM by itself cannot completely address the vast and growing number of machine learning operators. A RISC-V CPU is ideal for efficient programming and future-proofing of an CIM-based NPU.  The RISC-V architecture allows users to add custom instructions to encapsulate the CIM computing blocks, easing software development efforts.  Andes automates this instruction customization process with its automated COPILOT compiler.

Mr. Frankwell Lin, Chairman and CEO of Andes, says, “Andes is honored and excited to have Rain AI as its licensee and partner.  As the first RISC-V vector processor provider, we see CIM as an inevitable necessity to enable generative AI applications and therefore have focused on CIM customers.  To our knowledge, Rain AI has designed one of the most energy efficient matrix multiplication units using digital CIM technology, so we look forward to Rain AI unveiling its breakthrough solutions.”

Mr. William Passo, CEO of Rain AI, echoed this sentiment, stating, “It is rare to see a vendor who shares the same market and technology vision as us, has best-in-class RISC-V solutions for our technology needs, and can commit resources to help us accelerate our roadmap to significantly reduce the energy required for AI.  Running the most advanced models in any form factor is the future of AI, and we are now one step closer with Andes.”

Indeed, Rain AI further taps into Andes’ Custom Computing Business Unit (CCBU) to help accelerate the integration of Andes AX45MPV and the ACE/COPILOT instruction customization with on-site and remote consulting services. Andes’ CCBU is a small team of experts tasked to perform complex customizations and integrations for a few promising cutting-edge licensees. 

Both companies can share that AX45MPV and Andes’ unique RISC-V instruction customization solution, ACE/COPILOT both play pivotal roles to complement Rain AI’s groundbreaking CIM hardware, compiler, and runtime software to deliver scalable ML solutions for a variety of deployment points. Rain AI will unveil its accelerator solution in early 2025.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedInTwitterBilibili and YouTube! ! 

About Rain AI
Rain AI’s mission is to enable advanced and abundant AI everywhere by building the world’s most efficient AI hardware. It creates flexible solutions for generative AI inference and training utilizing novel compute-in-memory CIM technology, RISC-V processing cores, advanced packaging techniques, and optimized ML algorithms. By co-designing hardware with leading AI models, Rain AI sets new standards in AI efficiency and performance. Rain AI investors include Sam Altman, Dan Gross, and Y Combinator. For further information, visit http://www.rain.ai.

Continue ReadingRain AI Unveils Andes Technology as Its RISC-V Partner

Andes Technology Announced the QiLai SoC and the Voyager Development Board

May 30, 2024 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced the QiLai SoC and the Voyager development board to further accelerate the development and porting of large RISC-V applications.

The QiLai SoC chip includes high performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. The AndesCore™ AX45MP superscalar multicore contains a 2MB Level-2 cache, a coherence manger to manage Level-1 cache coherence, and a MMU (Memory Management Unit) for Linux based applications. The AndesCore™ NX27V vector processor with 512KB data cache supports a full range of RISC-V standard data types and Andes-enhanced data types optimized for AI workloads. The NX27V contains an efficient scalar unit and an out-of-order Vector Processing Unit (VPU) with 512-bit vector length (VLEN) and 512-bit data path width (DLEN), capable of generating up to 4 512-bit results per cycle. The NX27V can cooperate with the AX45MP cluster and make QiLai a heterogeneous software development platform where a Linux SMP system and an RTOS or bare-metal system can run simultaneously. The AX45MP and NX27V can run up to 2.2 GHz and 1.5GHz  respectively, and the total power consumption of the QiLai SoC is around 5W when running at its full speed.

The Voyager is a 9.6” x 9.6” Micro ATX form factor development board including a QiLai SoC, 16GB of DDR4 SIMM socket, JTAG debugger, USB to UART bridge, I2S Audio Codec, 16Mb SPI Flash for boot code, SD card socket, and several PCIe Gen4 slots that can bridge to many external devices such as GPU card and SSD. The supporting software includes the OpenSUSE Linux distribution, AndeSight™ toolchains, AndeSoft™ software stacks, and AndesAIRE™ NN SDK to convert AI/ML models to executables running on the NX27V vector processor.

“We are excited to announce the QiLai SoC which integrates our widely-adopted AndesCore™ AX45MP multicore and NX27V vector processor,” said Frankwell Lin, Andes Chairman and CEO. “These two processors have been licensed and silicon-proven by many customers though we are still pleased to see them working on our own silicon in the first cut. Manufactured at TSMC advanced 7nm process technology, the QiLai SoC and the Voyager development board demonstrate our commitment to enable the RISC-V software development in real time. Andes will keep its pure-play IP provider position, not going into chip business, this project is a response to provide better processor IP evaluation and application development purpose, and is an excellent resulting fruit from Andes GDR movement in 2021.”

“Andes has been asked by many partners and software developers for silicon-based platforms, where they can develop software for RISC-V more efficiently,” said Dr. Charlie Su, Andes President and CTO. “The Voyager board with the QiLai SoC is our response to that request and a great step towards enabling fast development and evaluation of a wide range of software for RISC-V, and further helps expand the RISC-V ecosystem.”

 

About Andes

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533SIN: US03420C2089ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion.

For more information, please visit www.andestech.com or contact info@andestech.com

Follow Andes on LinkedInTwitterBilibili and YouTube!

Continue ReadingAndes Technology Announced the QiLai SoC and the Voyager Development Board

Andes Technology and Arteris Partner To Accelerate RISC-V SoC Adoption

Highlights:
– Andes Technology and Arteris partnership aims to support the growing adoption of RISC-V SoCs by mutual customers.
– Focus is on high-performance/low-power RISC-V-based designs across a wide range of markets, including consumer electronics, communications, industrial applications and AI.
– The collaboration showcases integrated and optimized solutions with leading Andes RISC-V processor IPs and Arteris interconnect IP in silicon.

CAMPBELL, Calif. – May 21, 2024 – Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP that accelerates system-on-chip (SoC) creation and Andes Technology (TWSE: 6533), a founding and premier member of RISC-V International and a leading supplier of high-performance/low-power RISC-V processor IP, today announced their partnership to advance innovation for RISC-V based SoC designs for AI, 5G, networking, mobile, storage, AIoT and space applications.

The Andes QiLai RISC-V platform is a development board with a QiLai SoC featuring the Andes’ RISC-V processor IPs along with Arteris FlexNoC interconnect IP used for on-chip connectivity. The QiLai SoC integrates the Andes 64-bit AX45MP multiprocessor (four cores in a cluster) running at 2.2 GHz and the NX27V vector processor running at 1.5 GHz, using Arteris network-on-chip (NoC) interconnect IP with subsystems for PCIe, DDR, SRAM and General Purpose IO using the AMBA AXI protocol. The supporting software includes the OpenSUSE Linux distribution, AndeSight™ toolchains, AndeSoft™ software stacks and AndesAIRE™ NN SDK to convert AI/ML models to executables.

“Even though AndesCore™ AX45MP and NX27V processors are widely used, we are still pleased to see the QiLai SoC achieve first time right on new projects,” said Dr. Charlie Su, Andes Technology’s president and CTO. “Arteris NoC IP was the obvious choice for flexible, high-performance, top-level connectivity across the QiLai SoC. The QiLai platform enhances the rapid development and assessment of RISC-V software, accelerating the expansion of the RISC-V ecosystem.”

“We are excited to partner with Andes Technology and support the QiLai platform interoperability to further accelerate RISC-V technology mainstream adoption,” said Michal Siwinski, chief marketing officer at Arteris. “Our collaboration supports our mission to be the catalyst for SoC innovation so our mutual customers can focus on efficiently creating tomorrow’s breakthroughs.”

Arteris’ FlexNoC non-coherent NoC IP and Ncore cache-coherent NoC IP enable scalable, low latency and power-efficient on-chip communication to achieve superior performance in complex SoC designs. The technology facilitates the integration of high-performance, low-power CPU IPs, enhancing system functionality and interoperability, especially within the growing RISC-V ecosystem. This configurable and adaptable interconnect solution seamlessly interfaces with various components to mitigate risks and expedite time to market. By connecting well-tested CPU IP blocks, system designers can leverage Arteris NoC IPs to enhance the reliability and quality of next-generation SoCs.

Customers can request a devkit featuring the Andes QiLai RISC-V platform at sales@andestech.com. For more information on the partnership and respective products, please contact info@arteris.com and info@andestech.com.


About Arteris
Arteris is a leading provider of system IP for accelerating system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next. Learn more at arteris.com

About Andes Technology
Nineteen years in business and a founding premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533SIN: US03420C2089ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, TwitterBilibili and YouTube!

© 2004-2024 Arteris, Inc. All rights reserved worldwide. Arteris, Arteris IP, the Arteris IP logo, and the other Arteris marks found at https://www.arteris.com/trademarks are trademarks or registered trademarks of Arteris, Inc. or its subsidiaries. All other trademarks are the property of their respective owners.

Continue ReadingAndes Technology and Arteris Partner To Accelerate RISC-V SoC Adoption

晶心、經緯恒潤暨先楫半導體三方攜手 共築RISC-V AUTOSAR軟體生態

2024514日】晶心科技、經緯恒潤、先楫半導體聯合宣佈三方將開展合作,結合AndesCore™ RISC-V處理器系列、先楫半導體HPM6200全線產品和經緯恒潤的Vehicle OS軟體平台解決方案,共同致力於RISC-V在車規級晶片領域的生態。此次合作經緯恒潤AUTOSAR產品INTEWORK-EAS將適配先楫半導體HPM6200全線產品,對MCAL軟體適配和工程集成進行支援,協助先楫半導體構建AUTOSAR解決方案。經緯恒潤是目前少有的具備多款RISC-V車規級晶片適配經驗的AUTOSAR基礎軟體供應商,長久以來積極推動生態共建,願助力共同促進RISC-V車規級晶片生態繁榮。HPM6200全線產品共有12個產品型號,內置晶心科技AndesCoreTM D45單核和雙核RISC-V處理器,該系列產品具有高性能、即時性,應用領域包括新能源、儲能、工業自動化、電動車等。通過本次合作,先楫半導體的晶片產品將以功能更加完善、服務更加完整的狀態面向汽車電子不同應用場景,推動RISC-V技術在汽車電子領域的生態相容。未來,經緯恒潤與先楫半導體將保持合作,持續為反覆運算的新產品提供軟體平台解決方案。

INTEWORK-EAS是經緯恒潤自主研發,符合 AUTOSAR 標準的軟體產品,具備完整的 AUTOSAR 工具鏈,相容多種業內主流資料格式,如 DBC、LDF、PDX、ODX、ARXML 等,支援與協力廠商 MCAL 工具鏈無縫集成。解決方案涵蓋了嵌入式標準軟體、AUTOSAR 工具鏈、集成服務和培訓等各個方面的內容,旨在為OEM 和供應商提供穩定可靠、便捷易用的 AUTOSAR 平台。經緯恒潤重視軟硬體一體解決方案建設,自INTEWORK-EAS系列產品在國際知名晶片上經過廣泛量產驗證之後,經緯恒潤不斷深化與晶片企業之間的合作,共同向車規級市場提供更加完善的軟硬體一體解決方案。對於經緯恒潤而言,此次與先楫半導體HPM6200產品適配合作,將為其晶片生態合作圈增加新的重要成員,並使其保持在RISC-V生態適配方面的領先地位。

先楫半導體HPM6200採用晶心科技  D45核心,循序執行8級雙發射超純量技術,具有最佳化的儲存流水線設計以及進階分支預測功能,主頻達到 600 MHz,性能超過 3390 CoreMark和 1710 DMIPS,同時支援符合IEEE754的單/雙精度浮點運算單元(FPU)及RISC-V P (草案) 擴充指令 (DSP/SIMD)。D45系列核心也具有local memory支援的儲存子系統,以及可配置的指令及資料快取記憶體,對於HPM6000系列支援大量記憶體的SoC,可進一步提升其軟體效能。在應用市場而言, D45核心非常適合用於對回應時間和即時準確性特別要求的嵌入式應用產品。

HPM6200產品除了高算力RISC-V CPU,還整合一系列高性能外設以及外擴儲存。此外, HPM6200 系列還提供增強 PWM 控制系統,以及用於複雜信號生成的可程式設計邏輯陣列PLA。集成了AES-128/256、SHA-1/256 加速引擎和硬體金鑰管理器,HPM6200可以支援固件軟體簽名認證、加密啟動和加密執行,可防止非法的代碼替換、篡改或複製,進一步提升安全性。先楫半導體已完成ISO9001品質管制認證,和ISO 26262功能安全管理體系ASIL D認證,HPM6200 全線產品則通過AEC-Q100 G1認證,工作溫度範圍在-40~125℃。HPM6200與經緯恒潤AUTOSAR適配之後,將結合此軟體方案全力推廣於全球的汽車市場。

經緯恒潤嵌入式軟體版塊負責人張賀偉表示:「我們很高興與晶心科技和先楫半導體合作,三方聯合打造基於RISC-V的軟硬體一體化方案,一同為晶片生態建設推動前行。這個時代晶片快速迭代,正是發揮AUTOSAR Middleware軟體優勢的時候,我們的晶片適配能力樂於接受新硬體環境的挑戰,此次合作將再次證明這一點。未來,我們希望能夠和更多的合作夥伴一起提供集成化解決方案,促進汽車產業向未來發展。」

先楫半導體執行長曾勁濤表示:「晶心科技D45處理器能夠為先楫半導體超高速即時運算要求的MCU系列產品提供高效支援。在某些測試環境下,Andes CPU性能超越其他競品,表現優異,且經由晶心產品導入所提供的即時技術支援,協助我們成功並快速地完成HPM6000系列的成功Tape out,雙方團隊可謂完美地進行了一次緊密高效的合作。」「對於先楫半導體來說,此次適配經緯恒潤的AUTOSAR合作,這不僅意味著先楫半導體產品得到了業界的廣泛認可,更意味著內嵌Andes RISC-V核心的高性能微控制器產品在新能源電動汽車領域的應用前景得到了進一步拓展。」

晶心科總經理暨技術長蘇泓萌博士表示:「晶心科技D45配合先楫半導體為開發者提供完備的生態系統,客戶得以設計出更高效能、和更多功能的軟體,因而得以領先同業推出內嵌高效能RISC-V核心之MCU安全解決方案,此充分展現其團隊的超高效率及卓越的研發能力。」「經緯恒潤與先楫半導體的合作為行業樹立了典範,也為後續的合作提供了寶貴經驗。我們期待未來能夠看到更多類似的合作,共同推動汽車電子產業的繁榮發展。」

 

關於經緯恒潤 (HiRain Technology)
經緯恒潤成立於2003年,專注於為汽車、無人運輸等領域的客戶提供電子產品、研發服務和高級別智慧駕駛整體解決方案。總部位於北京,並在天津、南通、馬來西亞有研發中心和現代化工廠,形成了完善的研發、生產、行銷、服務體系。本著「價值創新、服務客戶」的理念,公司堅持 「專業聚焦」、「技術領先」和「平台化發展」的戰略,致力於成為國際一流綜合型的電子系統科技服務商、智慧網聯汽車全棧式解決方案供應商,以及高級別智慧駕駛MaaS解決方案領導者。經緯恒潤是目前少數能夠實現覆蓋智慧駕駛電子產品、研發服務及解決方案之全棧式解決方案的供應商。未來,經緯恒潤將緊跟汽車行業發展大勢,堅持自主創新,努力為國內外客戶提供優質的產品和服務,為汽車行業的發展貢獻自己的一份力量。更多關於經緯恒潤的資訊,請訪問https://www.hirain.com/

關於先楫半導體 (HPMicro Semiconductor)
先楫半導體是一家致力於高性能嵌入式解決方案的半導體公司,產品覆蓋微控制器、微處理器和周邊晶片,以及配套的開發工具和生態系統。 公司成立於2020年6月,總部坐落于上海市張江高科技園區,幷在天津、深圳、蘇州和杭州均設立分公司。 核心團隊來自世界知名半導體公司管理團隊,具有15年以上且超過20個SoC豐富的研發及管理經驗。先楫半導體以產品品質為本,所有產品均通過嚴格的可靠性測試。目前已經量產的高性能通用MCU產品系列包含HPM6700/6400、HPM6300、HPM6200、HPM5300及HPM6800,性能領先國際同類產品幷通過AEC-Q100認證。公司已完成ISO9001品質管制認證和ISO 26262/IEC61508功能安全管理體系雙認證,全力服務工業、汽車和新能源市場。先楫半導體將與世界知名晶圓廠、封裝測試廠及其它戰略合作夥伴一起,共同推進互聯網,工業自動化,汽車電子等半導體領域的技術創新。更多關於先楫半導體的資訊,請訪問www.hpmicro.com

關於晶心科技 (Andes Technology)
晶心科技股份有限公司于2005年成立於新竹科學園區,2017年於臺灣證交所上市 (TWSE: 6533 SIN: US03420C2089ISIN: US03420C1099)。晶心是RISC-V國際協會的創始首席會員,也是第一家推出商用RISC-V向量處理器的主流CPU供應商。為滿足當今電子設備的嚴格要求,晶心提供可配置性高的32/64位元高效能CPU核心,包含DSP、FPU、Vector、超純量  (Superscalar)、亂序執行  (Out-of-Order)、多核心及車用系列,可應用於各式SoC與應用場景。晶心並提供功能齊全的整合開發環境和全面的軟/硬體解決方案,可幫助客戶在短時間內創新其SoC設計。截至2023年底,Andes-Embedded™ SoC累計出貨量已超過140億顆。 欲瞭解更多資訊,請訪問  https://www.andestech.com 。請立即透過LinkedInTwitterBilibili以及YouTube追蹤晶心最新消息。

Continue Reading晶心、經緯恒潤暨先楫半導體三方攜手 共築RISC-V AUTOSAR軟體生態

TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP

To enable SoC design teams and Automotive software developers to build optimized and certifiable software solutions.

Munich, Germany – March 27, 2024 – TASKING proudly announces that its ISO 26262 (functional safety) and ISO/SAE 21434 (cybersecurity) compliant compilers now fully support the Andes FuSa certified RISC-V IP. This advancement expands TASKING’s RISC-V tool suite to include compilation, debugging, performance tuning, timing, and coverage analysis tools, providing a comprehensive solution for automotive systems development.


This milestone signifies a significant stride in empowering SoC design teams and automotive software developers to craft highly optimized and certifiable RISC-V based solutions. The newly introduced RISC-V compiler, compliant with ASIL D standards, seamlessly supports both current and forthcoming FuSa certified Andes RISC-V cores. Noteworthy is the compiler’s adaptability to the RISC-V ISA and its extensions, including Andes-specific extensions, ensuring dynamic optimization tailored to the target device, thereby enhancing efficiency and performance.


Andes Technology has achieved remarkable milestones in the automotive market with the introduction of the world’s first RISC-V ISO-26262 fully compliant core, N25F-SE, in 2022. Subsequently, Andes is about to unveil the ASIL-B certified D25F-SE equipped with the RISC-V SIMD/DSP P-extension support (draft), enabling efficient processing of multiple data in a single instruction. Looking ahead, Andes is set to launch processors meeting the ASIL-D standard, including the compact and secure D23-SE, the high-performance D45-SE, and the forthcoming ADAS-capable core in AX60 Series. These advancements underscore Andes’ ability to provide tailored solutions for diverse automotive applications, highlighting its leading expertise in the automotive RISC-V IP market.

 

“AndesCore™ RISC-V IP, certified with ISO 26262, presents a solid portfolio of automotive processor solution offering unparalleled level of flexibility and efficiency benefits to silicon development,” said Samuel Chiang, Deputy Marketing Director of Andes, “Our partnership with Tasking enables customers in the automotive industry to expedite their development processes, enhancing the performance and robustness of safety-critical RISC-V applications.”


Commenting on the collaboration, Gerard Vink, TASKING’s RISC-V lead, expressed enthusiasm, stating, “We are thrilled to collaborate with Andes and their ecosystem partners. The seamless interoperability of our tools with Andes RISC-V IP across development platforms ranging from virtual prototype to silicon implementations underscores our commitment to providing comprehensive lifecycle support for SoC development teams. Leveraging TASKING’s advanced FuSa and Cybersecurity processes, our users can fast-track compliance efforts, accelerating the time-to-market of RISC-V based automotive software solutions.”

 

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533SIN: US03420C2089ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety, and/or multicore capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedInFacebookXBilibili and YouTube


About TASKING
TASKING is a leading provider of development tools headquartered in Munich, Germany, offering high-performance, high quality, safety & security-oriented embedded software development tools for multi-core architectures.,


TASKING’s development tools are used by automotive manufacturers and suppliers, as well as in adjacent markets around the world to realize high-performance applications in safety-critical areas.


The TASKING Embedded Software Development solutions provide an industry-leading ecosystem for your entire software development process. Each TASKING compiler is designed for a certain architecture and meets the specific requirements of your industry, including automotive, industrial, telecommunications and datacom.


As the recognized leader in high-quality, feature- and safety-compliant embedded software development tools, TASKING enables you to create code with best-in-class size and performance with compilers, debuggers and RTOS support for industry-leading microprocessors and microcontrollers.


Since February 2021, TASKING has been majority-owned by financial investor FSN Capital, which has put the group on a long-term growth path following a successful carve-out. For more information visit www.tasking.com or follow us on https://www.linkedin.com/company/tasking-inc.

Continue ReadingTASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP

晶心科技營業額連續七年成長 年度收入已突破十億新臺幣

據SHD市場報告顯示,晶心科技是RISC-V CPU IP的No.1供應商

【台灣新竹】 2024年3月21日】-晶心科技(TWSE:6533)自2017年首次公開發行以來,在過去七年間營業額成長了5倍,鞏固了其作為處理器IP領域領導企業的地位。晶心投入資金及研發人力加快高階產品面世,確保長期競爭力及保持市場領先地位,預計具有競爭力的產品組合將創造下一波營收高峰。

憑藉對市場動態和技術趨勢的密切觀察及果斷的決策,晶心科技靈活調整其戰略定位,並抓住新興機遇。例如將其第三代自有指令集架構AndeStar™ V3,在2016年升級第五代AndeStar™ V5時,引入RISC -V架構。或者在RISC-V 打入主流ISA架構的趨勢出現後,決定加速推出高階產品以搶佔相關市場如AI加速、RISC-V車用、以及應用處理器晶片設計。在2023年,半導體產業面臨庫存壓力的狀況下,內嵌AndesCore™的SoC累計出貨量仍突破了140億顆。根據2024年1月發布的SHD行銷報告,晶心科技在RISC-V IP供應商中,市場占有率高達30%,為全球第一大RISC-V CPU IP供應商。

SHD report

(圖片來源: SHD 2024 RISC-V Market Analysis)

2023年,晶心科技多元化的產品組合引起了市場的強烈共鳴,並促進了其業績的持續增長。晶心科技成功推出市場上第一個RISC-V向量處理器-AndesCore™ AX45MPV,以及N25F-SE–引領RISC-V行業革命、ISO 26262全面合規的車規核心。晶心科技亦進軍應用處理器市場,推出了高階的亂序處理器(OOO)-AndesCore™AX65,並針對精簡、高效和安全的應用,發布了AndesCore™ D23 和AndesCore™ N225。在CPU IP之外,晶心還建立了新的AI產品線AndesAIRE™ (Andes AI Runs Everywhere),為邊緣和端點推理提供了全面的硬體及軟體人工智慧整合解決方案。

晶心科技對客戶滿意度的堅定承諾強化了與客戶的關係,並了深化了其領導市場的地位。晶心產品的潛在市場涵蓋廣泛,包括AI/ML、5G通訊、FPGA、影像處理、物聯網、微控制器/微處理器、感測器、儲存、TDDI和無線連接。

展望未來,晶心科技將持續致力於創新、客戶滿意度以及不斷適應動態CPU IP授權市場。 以下是驅動晶心成長的一系列關鍵因素:
人工智慧和高效能運算應用的擴展:人工智慧和高效能運算(HPC)應用的需求持續增長,加上對專用SoC的需求,是晶心的主要推動力之一。提供配備ACE™(Andes Automated Custom Extension)的處理器,滿足 AI 和 HPC 工作負載大量且嚴格的要求,為晶心的市場成長做出了重大貢獻。

對車規級(ISO 262626) SoC的需求增加:隨著汽車電子產業的快速發展,對符合ISO 262626標準的車規級SoC的需求不斷增加。晶心科技把握了這一趨勢,積極滿足對車規級解決方案的增長需求。通過提供專為滿足汽車行業嚴格安全和可靠性要求的處理器,晶心科技的產品已處在RISC-V市場之領先地位,領先完成多項認證,可滿足這個日益擴張中的市場,進一步提高其成功量產率及市場滲透率。

RISC-V生態系統的日趨成熟:通過積極參與RISC-V 國際協會和開發社群,並作為最高等級會員及活動贊助商,晶心科技為RISC-V生態系統的快速擴展做出貢獻。 透過這些努力,晶心始終處於RISC-V開發的最前線,促進了一個對公司自身和RISC-V生態系都有利的良性循環。

多核異構SoC的興起:從人工智慧物聯網、邊緣計算和資料中心等各個新興領域的應用結構的日益複雜,導致了多核異構SoCs的成長。晶心科技的策略重點是開發多樣化的產品組合,以符合多核異構SoCs的需求。晶心多樣化CPU IP 組合提供了當今應用程式需求的性能和靈活性。

「晶心科技過去七年的持續成長,印證了我們引領行業趨勢的堅定決心以及對客戶的承諾,」晶心科技董事長暨執行長林志明表示。「我們仍然致力於透過尖端解決方案塑造 CPU IP 授權市場的未來。」

「晶心科技以『驅動創新』為座右銘,制定未來之產品路線圖。一方面,我們正在開發突破性能極限的高端產品;另一方面,我們繼續提供強大的精簡型處理器,以提高能效和安全性。」 晶心科技總經理暨技術長蘇泓萌博士提到。「將我們的專業知識與這個不斷發展的行業的需求相結合,我們傑出的團隊以及與客戶的有效合作將繼續推動我們前行,塑造未來高性能、高效率的運算,滿足汽車SoC嚴格的安全要求,並實現不斷湧現的人工智慧需求。」

 

關於Andes RISC-V CON新竹場
Andes RISC-V CON是由晶心科技主辦和合作夥伴贊助的年度RISC-V技術論壇。2024年,新竹場將於3月28日於新竹晶宴會館御豐館舉行。2024年的主題是【深探車用、AI、應用處理器與安全技術趨勢】,將介紹RISC-V市場動態及發展趨勢,並分享晶心如何協助RISC-V生態系統實現創新技術的多樣化應用。本次展示重點將放在四個產業高度關注的應用領域上:人工智慧/機器學習、汽車電子、應用處理器和資安。本次研討會邀請到眾多RISC-V生態系夥伴進行專題演講及現場展示。
欲瞭解更多資訊,請查看Andes RISC-V CON的官方網站http://bit.ly/andes2024https://www.andestech.com/Andes_RISC-V_CON_2024_TW/

關於晶心科技(Andes Technology)
晶心科技股份有限公司於2005年成立於新竹科學園區,2017年於臺灣證交所上市(TWSE: 6533 SIN: US03420C2089; ISIN: US03420C1099)。晶心是RISC-V國際協會的創始首席會員,也是第一家推出商用RISC-V向量處理器的主流CPU供應商。為滿足當今電子設備的嚴格要求,晶心提供可配置性高的32/64位元高效能CPU核心,包含DSP、FPU、Vector、超純量(Superscalar)、亂序執行(Out-of-Order)、多核心及功能安全系列,可應用於各式SoC與應用場景。晶心並提供功能齊全的整合開發環境和全面的軟/硬體解決方案,可説明客戶在短時間內創新其SoC設計。截至2023年底,嵌入AndesCore™ 的SoC累積總出貨量已達140億顆。欲瞭解更多資訊,請訪問  https://www.andestech.com
請立即透過LinkedInXBilibili以及YouTube追蹤晶心最新消息。

Continue Reading晶心科技營業額連續七年成長 年度收入已突破十億新臺幣

晶心科技將於3/28舉辦年度研討會ANDES RISC-V CON
看好RISC-V於AI、車用電子、應用處理器及安全技術的市場動向

【台灣新竹】— 2024年3月21日 — 近年來,RISC-V 在車用電子、資安技術和人工智慧等先進領域正經歷快速擴展,在高階應用處理器的發展也備受期待。根據市場研究機構SHD Group預測,到2030年,基於 RISC-V 的 SoC 出貨量將急遽增加至162億顆,相應營收更預計達到920億美元,複合年增長率分別高達44%和47%。由此可知, RISC-V 架構的顯著增長趨勢,進一步推動了一場技術革命的引爆。

隨著 RISC-V 成為市場主流解決方案,晶心深耕 RISC-V 領域多年,深刻了解其開放、精簡及可擴充的彈性配置特性而深受眾多領導廠商青睞。作為 RISC-V CPU 核心的領導品牌,並且更深入探討 RISC-V 在各項應用場景的可能性,晶心科技於 3 月 28 日在新竹晶宴會館御豐館舉辦「晶心科技 RISC-V CON :深探車用、AI、應用處理器與安全技術趨勢」年度研討會。活動將以實體與線上同步呈現,聚集行業專家和領導品牌,並深入介紹 RISC-V 在市場中的變動情形和未來發展趨勢。期待透過晶心豐富的經驗,協助生態圈夥伴一同發掘 RISC-V 的潛力,贏得競爭優勢。

晶心科技邀請到TSMC擔任開場嘉賓,展現Foundry廠對RISC-V生態系統的堅強支持。同時,晶心科技的董事長暨執行長林志明先生將以「RISC-V 豐富的解決方案帶來亮麗未來」為題,探討RISC-V指令集標準作為處理器矽智財、平台與軟硬體環境生態系統的基礎,導引了豐富的晶片與系統產品發展,在3A1S (AI, Application Processor, Automotive, Security) 的大會主題趨勢中所扮演角色,從而引領半導體產業亮麗的未來。

本次活動將深度探討應用處理器、車用電子、人工智慧和安全技術四大熱門應用領域市場與技術趨勢。首先,由晶心科技總經理蘇泓萌博士帶領,深入剖析RISC-V當作處理器在各主流應用的現況,並分享對高階及應用處理器市場RISC-V技術發展與機會的獨到見解。接著,隨著電動車技術的日趨成熟,晶心如何提供符合ISO26262全面合規之RISC-V設計,快速協助客戶進入車規市場。第三個主題將聚焦於AI領域,提供基於Transformer計算的硬軟整合解決方案。最後,研討會將深入探討資訊安全市場的趨勢,並闡述在RISC-V框架下建構可信執行環境的方法。

ANDES RISC-V CON新竹場也邀請到眾多RISC-V生態夥伴參與專題演講及現場展示,包括全球領先的NAND快閃記憶體控制器IC和儲存解決方案提供商群聯電子(Phison)、DDR與安全設計IP的授權大廠Rambus、自動化程式碼分析和軟體測試廠商LDRA,和嵌入式軟體開發工具領導供應商Tasking,均以專題演講方式分享其在RISC-V領域的最新應用。此外,其他參與本次活動的夥伴還包括電子設計領域的翹楚Cadence、編譯器軟體大廠IAR、eFPGA IP的領先供應商Menta、業內知名EDA解決方案專家S2C、嵌入式解決方案的系統整合廠商新華電腦,以及主導並協助RISC-V 產官學界合作的台灣RISC-V聯盟等,都將於現場展示其基於RISC-V技術開發的最新產品與解決方案。這絕對是一場不容錯過的RISC-V盛會,敬請立即線上免費報名。

活動網頁:  http://bit.ly/andes2024

實體場報名: https://bit.ly/andes2024a

線上場報名: https://bit.ly/Andes2024b

關於Andes RISC-V CON新竹場

Andes RISC-V CON是由晶心科技和合作夥伴贊助的年度RISC-V技術論壇。2024年,新竹場將於3月28日於新竹晶宴會館御豐館舉行。2024年的主題是【深探車用、AI、應用處理器與安全技術趨勢】,將介紹RISC-V市場動態及發展趨勢,並分享晶心如何協助RISC-V生態系統實現創新技術的多樣化應用。本次展示重點將放在四個產業高度關注的應用領域上:人工智慧/機器學習、汽車電子、應用處理器和資安。本次研討會邀請到眾多RISC-V生態系夥伴進行專題演講及現場展示。

欲瞭解更多資訊,請查看Andes RISC-V CON的官方網站http://bit.ly/andes2024https://www.andestech.com/Andes_RISC-V_CON_2024_TW/

 關於晶心科技(Andes Technology)

晶心科技股份有限公司於2005年成立於新竹科學園區,2017年於臺灣證交所上市(TWSE: 6533 SIN: US03420C2089; ISIN: US03420C1099)。晶心是RISC-V國際協會的創始首席會員,也是第一家推出商用RISC-V向量處理器的主流CPU供應商。為滿足當今電子設備的嚴格要求,晶心提供可配置性高的32/64位元高效能CPU核心,包含DSP、FPU、Vector、超純量(Superscalar)、亂序執行(Out-of-Order)、多核心及功能安全系列,可應用於各式SoC與應用場景。晶心並提供功能齊全的整合開發環境和全面的軟/硬體解決方案,可説明客戶在短時間內創新其SoC設計。截至2023年底,嵌入AndesCore™ 的SoC累積總出貨量已達140億顆。欲瞭解更多資訊,請訪問  https://www.andestech.com 。請立即透過LinkedInXBilibili以及YouTube追蹤晶心最新消息。

Continue Reading晶心科技將於3/28舉辦年度研討會ANDES RISC-V CON
看好RISC-V於AI、車用電子、應用處理器及安全技術的市場動向

Andes and MachineWare Collaborate on Early RISC-V Software Development for AndesCore™ AX45MPV

Aachen, Germany and Hsinchu, Taiwan, February 27th 2024
MachineWare GmbH and Andes Technology (TWSE:6533), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announce an exciting new chapter in their collaboration, marked by a strategic partnership. This synergistic alliance is geared towards the highly innovative AndesCoreAX45MPV, a cutting-edge multi-core RISC-V vector processor tailored for AI workload acceleration and the application level. In this joint effort, MachineWare lends its support by seamlessly integrating the AX45MPV into their SIM-V high-performance simulation solution. This integration proves invaluable for software developers, enabling them to efficiently handle intricate AI and Linux stack related workloads. The result is a platform that streamlines development, testing, and software verification well in advance of physical prototypes emerging from the fabrication process. This partnership underscores the mutual commitment of MachineWare and Andes Technology to advancing processor technology.

Introducing SIM-V, an offering from MachineWare that holds immense value for developers in the RISC-V landscape. With SIM-V, developers gain the power to thoroughly test and verify their RISC-V-based systems and software applications long before first prototypes are back from the fab. At its core, SIM-V provides a fast Instruction Set Simulator (ISS) that supports all RISC-V standard extensions. One of SIM-V‘s notable strengths is its user-friendly customizability. Through a straightforward extension SDK, developers can swiftly integrate custom instructions, registers, and other elements into the simulator to get instant feedback on their design choices. What makes SIM-V truly special is its SystemC TLM-2.0 integration. This unique combination empowers users to seamlessly introduce their IP models into full system simulation environments, enhancing the versatility of the platform.

The AndesCore™ AX45MPV is a 64-bit 8-stage dual-issue multicore RISC-V vector processor. It incorporates RISC-V GCBP* (*P is a draft version) extensions, and supports SMP Linux with MMU (Memory Management Unit) and up to 48-bit virtual addresses. In addition, it can be configured to up to eight cores with a cache coherence manager and up to 8MB shared L2 cache memory in a cluster. The Vector Processing Unit (VPU) of the AX45MPV implements RISC-V Vector Extension (RVV) version 1.0. It supports configurations of up to 1024-bit vector width (VLEN) and datapath width (DLEN). The AX45MPV is excellent for computations involving large arrays of data such as computer vision, digital signal processing, image processing, machine/deep learning, and scientific computing.

Figure 1: Invoking SIM-V with the AX45MPV configuration.

“We are delighted to join forces with Andes to support the AX45MPV processor in SIM-V,” said Lukas Jünger, Managing Director at MachineWare. “The incorporation of the AX45MPV model enables our common customers to develop RISC-V Linux and AI software stacks and verify their functionality in minutes. This will eliminate bugs and elevate software quality all the while making the overall development process more efficient.”

“Andes’ collaboration with MachineWare is consistent with our continuous effort to broaden RISC-V ecosystem for easy adoption of high-performance simulation tools,” said Samuel Chiang, deputy marketing director of Andes Technology. “We are excited to come together with MachineWare to drive the expansion of the RISC-V ecosystem. And we believe RISC-V’s instruction set architecture will increase innovation and has the potential to transform the AI market.”

About MachineWare GmbH
Founded in 2022 in Aachen, Germany, MachineWare leverages decades of experience in system level simulation and high-performance simulation tooling. Visit https://www.machineware.de/ for more details.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, automotive and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com . Follow Andes on LinkedInTwitterBilibili and YouTube!

About ANDES RISC-V CON
ANDES RISC- V CON is the annual RISC-V technology forum of Andes Technology. In 2024, the Hsinchu session will be held at Amazing Hall Yufeng on March 28; the Shanghai session will be held at DoubleTree by Hilton Hotel Shanghai – Pudong on April 9; the Shenzhen session will be held at Grand Mercure Shenzhen Oriental Ginza Hotel on April 11. The theme of this year is “ANDES RISC-V CON: Deep Dive into Automotive/ AI/ Application Processors and Security Trends.” It will introduce the flexible RISC-V that revolutionizes emerging applications and share Andes latest breakthroughs and innovations in RISC-V. Four popular applications will be focused on: AI, automotive electronics, security and RISC-V’s new field, application processor. Many RISC-V ecosystem partners, including TSMC, are invited to deliver talks and on-site demonstrations.

For more event details and free registration, please visit the official website of the events:


About RISC-V
The RISC-V open architecture ISA is under the governance of RISC-V International. Visit https://riscv.org for more details.


MachineWare Contact
Lukas Jünger, Managing Director
E-mail: lukas@mwa.re

Andes Technology Contact
Jonah McLeod, Press Contact, Andes Technology
Tel: +1-510-449-8634
E-mail: Jonahm@andestech.com

Continue ReadingAndes and MachineWare Collaborate on Early RISC-V Software Development for AndesCore™ AX45MPV

晶心科技與元視芯智能科技合作打造全球首次採用RISC-V IP SoC的車規級CMOS圖像感測器產品

台灣新竹— 2024222 —  RISC-V IP供應商晶心科技(TWSE:6533)與邊緣運算晶片供應商元視芯智能科技共同宣佈,元視芯 MAT系列作為全球首次採用RISC-V IP SoC的車規級CMOS圖像感測器系列晶片產品,採用了晶心AndesCore™ N25F-SE處理器,按照ISO26262功能安全流程標準設計,產品達到ASIL-B 等級,並遵循AEC-Q100 Grade 2,實現高水準的安全性和可靠性。 透過使用 HDR 等技術,可以在簡單、經濟且高效的系統中實現高階成像性能。 該系列產品不僅達到了高動態範圍、高靈敏度、高色彩還原的成像效果,而且滿足了ADAS決策的應用需求。

 晶心科技的N25F-SE32位元RISC-V CPU核心,可支援標準IMACFD指令集,其中包括高效整數指令集和單/雙精度浮點運算指令集。 N25F-SE的高效五級流水線在高操作頻率和簡化設計之間實現良好的平衡。 它還具有豐富的可配置選項和靈活的介面配置,大大簡化SoC的開發。 此外,N25F-SE還獲得ISO 26262 ASIL-B全面合規(Full compliance)認證,使影像感測器晶片能夠滿足車規級安全要求。 對於元視芯汽車級晶片的開發,N25F-SE及其安全套件 (Safety Package) 提供良好的CPU解決方案,加上晶心的技術支援,大大縮短了晶片開發時間。

 元視芯擁有一流的創新研發能力,開發包括橫向溢出集成式電容(LOFIC, Lateral Overflow Integration Capacitor)結合雙轉換增益(DCG, Dual Conversion Gain)、高動態範圍 (HDR, High-Dynamic Range)在內的多項前沿技術,滿足智能汽車視覺應用對的高品質影像的需求。 MAT Series 1MP CMOS影像感測器晶片具有低功耗、高動態範圍(HDR)等特性,其有效影像解析度為1280 H * 960 V,可支援高達60fps @120dB的高動態範圍影像輸出。 另一顆MAT Series 3MP晶片具有低功耗、超高動態範圍(HDR),並兼具on-chip ISPLFM (LED Flicker Mitigation) 等多種功能,其有效影像解析度為1920 H * 1536 V,最高可支援60fps幀率,動態範圍可達業界領先的140dB+ 這些晶片可為智能汽車應用提供可靠的高品質影像資訊。

 N25F-SE提供安全套件,其中包括安全手冊(Safety Manual)、安全分析報告 (Safety Analysis Report)和開發介面概要 (Development Interface Outline)N25F-SE及其安全套件是有效、高性能和靈活的汽車解決方案,它大大縮短汽車級 SoC開發時間並符合ISO 26262 標準。」 晶心科技總經理暨-CTO蘇泓萌博士表示:「我們很高興N25F-SEIP和安全套件,有效幫助元視芯縮短其兩款車規級晶片的開發時間。我們也期待未來兩家公司之間有更多的合作,創造更多創新產品。」

 元視芯智能科技CTO鄭健華表示:「在汽車ADAS應用使用的各種感測器之中,視覺影像處理晶片尤其重要。 一旦影像不夠準確和及時,將直接導致後端演算法的判斷出現錯誤,因此對HDR性能要求極高。元視芯的LOFIC+DCG HDR技術可達到140dB+的超高動態範圍,滿足汽車ADAS領域的實際應用需求。 我們很榮幸與晶心科技在兩款高效能晶片上緊密合作,採用全球首款符合功能安全標準的ISO 26262認證RISC-V核心N25F-SE,因此,我們得以縮短產品的開發時間並實現了功能安全目標。」

 關於晶心科技

晶心科技股份有限公司於2005年成立於新竹科學園區,2017年於臺灣證交所上市 (TWSE: 6533 SIN: US03420C2089ISIN: US03420C1099)。晶心是RISC-V國際協會的創始首席會員,也是第一家推出商用RISC-V向量處理器的主流CPU供應商。為滿足當今電子設備的嚴格要求,晶心提供可配置性高的32/64位元高效能CPU核心,包含DSPFPUVector、超純量 (Superscalar)、亂序執行 (Out-of-Order)、多核心及車用系列,可應用於各式SoC與應用場景。晶心並提供功能齊全的整合開發環境和全面的軟/硬體解決方案,可説明客戶在短時間內創新其SoC設計。截至2023年底,Andes-Embedded™ SoC累計出貨量已超過140億顆。 欲瞭解更多資訊,請訪問  https://www.andestech.com 。請立即透過LinkedInTwitterBilibili以及YouTube追蹤晶心最新消息。

 關於元視芯智能科技

元視芯智能科技成立於2021年,憑藉出色的創新研發能力和對卓越工藝的追求,在短短2年時間就迅速佈局汽車和手機雙產業賽道。 元視芯的汽車產品涵蓋電子後視鏡、360度環視、高階駕駛輔助系統(ADAS)等諸多車載應用。 在自主研發的超低雜訊和功耗讀取電路,以及獨特的MetaHDR高動態範圍等技術的支援下,為行業提供低功耗、高感度、高動態、高幀率的影像感測器,賦能智能車載應用。 有關元視芯的更多資訊,請參閱官方網站http://www.mtsilicon.com/

 關於ANDES RISC-V CON

ANDES RISC-V CON是晶心科技一年一度的RISC-V技術論壇。 2024年新竹場次將於328()在新竹晶宴會館御豐館舉行。2024年的主題是「深探車用、AI、應用處理器與安全技術趨勢」。介紹RISC-V市場動態及發展趨勢,並討論近來晶心推出的全方位產品組合。邀請包括台積電在內的眾多RISC-V生態合作夥伴進行演講和現場展示。免費報名請參考Andes RISC-V CON官網:https://www.andestech.com/Andes_RISC-V_CON_2024_TW/

Continue Reading晶心科技與元視芯智能科技合作打造全球首次採用RISC-V IP SoC的車規級CMOS圖像感測器產品