Learn the Latest on RISC-V and Vector Processing at All Six Andes Technology Corporation’s Presentations at the 2020 RISC-V Summit
SAN JOSE, CA – November 05, 2020 – Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding Premier member of RISC-V International will make six presentations at the virtual RISC-V Summit from December 8 to 10, 2020.
Andes CTO and Executive VP, Charlie Hong-Men Su, will give an overview and update on “Andes RISC-V Processor IP Solutions.” Andes Senior Director of Architecture Div., Chuan-Hua Chang, will present “AndesClarity: a Performance & Bottleneck Analyzer for RISC-V Vector Processors.” Paul Ku, Deputy Technical Director of Architecture Div., will introduce “Building a Secure Platform with the Enhanced IOPMP.”
The SoC industry has seen fast-growing and diversified demands for a wide range of RISC-V based products: from tiny low-power MCUs for consumer devices, to chips powering enterprise-grade products and datacenter servers; from one power-efficient core to a thousand GHz+ cores working cohesively. Charlie Su will explain the rich portfolio of AndesCore™ RISC-V processor IPs already populating these SoCs: compact single-issue cacheless cores to feature-rich Linux-capable superscalar cores, cache-coherence multicores, and cores capable of processing floating-point and DSP data to those crunching a large volume of vector data. He will also update RISC-V IPs newly added to Andes processor portfolio, the associated software support and their performance data.
Additionally, Deputy Software Manager, Shao-Chung Wang, will present “Extending Multicore Programming Framework for Vector Extension.” Ding-Kai Huang, VLSI Manager, will discuss “Enhancing Verification Coverage for RISC-V Vector Extension Using RISCV-DV,” co-authored with Tao Liu from Google. Andes Principal Architect, Thang Tran, will hold a 3-hour master class entitled “RISC-V Vector Extension Demystified.”
For more information, please visit the RISC-V Summit website.
- Charlie Su’s presentation “Andes RISC-V Processor IP Solutions” will occur on December 8 from 3:00 to 3:20 pm.
- Shao-Chung Wang will introduce “Extending Multicore Programming Framework for Vector Extension” on December 8 from 3:20 to 3:30 pm.
- Ding-Kai Huang will present “Enhancing Verification Coverage for RISC-V Vector Extension Using RISCV-DV” on December 9 from 12:00 to 12:20 pm.
- Paul Ku’s presentation “Building a Secure Platform with the Enhanced IOPMP” will take place on December 9 from 2:30 to 2:50 pm.
- Chuan-Hua Chang will present “AndesClarity: a Performance & Bottleneck Analyzer for RISC-V Vector Processors” on December 9 from 3:30 to 3:50.
- Thang Tran’s tutorial “RISC-V Vector Extension Demystified” will take place on December 10 from 2:00 to 5:00 pm.
About Andes Technology Corp.
Andes Technology Corporation is a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment that serves the rapidly growing global market for embedded system applications. As the founding Premier member of RISC-V International, Andes is the first mainstream CPU vendor that adopted the RISC-V as the base of its fifth-generation architecture, the AndeStar™ V5. To meet the demanding requirements of today’s electronic devices, Andes delivers highly configurable and performance-efficient CPU cores. They come with full-featured integrated development environment and comprehensive software/hardware solutions to help designers innovate their SoCs in a shorter time to market. In 2019, the volume of SoCs Embedded with Andes CPUs surpassed the 1.5-billion mark. Andes Technology’s comprehensive RISC-V CPU families range from the entry-level 32-bit N22, mid-range 32-bit N25F/D25F/A25/A27 and 64-bit NX25F/AX25/AX27, to the high-end multicore A(X)25MP and vector processor NX27V. Coming soon is the superscalar 45 series. For more information, please visit http://www.andestech.com/
Telink and Andes Announce the TLSR9 SoC with RISC-V Processor
SHANGHAI, CHINA – November 2, 2020 – Telink Semiconductor and Andes Technology are proud to introduce the new connectivity system on a chip (SoC) for Telink’s latest product line, the TLSR9 series. Powered by the Andes RISC-V core D25F, the TLSR9 series is designed for the next generation of hearables, wearables, and other high-performance IoT applications. Thanks to the companies’ partnership with IAR Systems, IoT designers will also have access to the powerful development toolchain IAR Embedded Workbench for flexible product development.
Enabling Innovative New IoT Products
The Telink TLSR9 series is the latest addition to Telink’s line of complete connectivity solutions, and it is designed to maximize device performance and minimize time to market. The TLSR9 series is designed using Andes’ latest AndeStar™ V5 Instruction Set Architecture (ISA), which is compliant to the RISC-V technology. As an open source instruction set architecture (ISA), RISC-V offers developers a great depth of design knowledge and facilitates more innovative and secure processor design.
The TLSR9 SoC features Andes 32-bit RISC-V processor D25F and is the world’s first SoC which adopts RISC-V DSP/SIMD P-extension that is ideal for a variety of mainstream audio, wearables and IoT development needs. The D25F has an efficient 5-stage pipeline and delivers the leading performance of 2.59 DMIPS/MHz and 3.54 CoreMark/MHz at its class. With RISC-V P-extension (RVP), it significantly increases the efficiency for small volume of data computation, and makes the compact AI/ML applications possible on the edge devices. It has been collected that 14.3x speedup of CIFAR-10 AI models, which is a typical image classification technology, and 8.9x speedup of keyword spotting technology, which consumed only dozens of million cycles per inference. Furthermore, the standard JTAG and Andes 2-wire serial debugging port helps to reduce the pin cost.
“We are excited to announce the news,” said Dr. Wenjun Sheng, CEO of Telink Semiconductor.“Telink has always been dedicated to building the future of the Internet of Things and consumer electronics. That means continuously exploring new ways to make chips that are at once more powerful and easier to put into action. By partnering with Andes Technology and IAR Systems to provide a top-notch processor and IDE for our new TLSR9 product line, we are committed to reducing the difficulty of application development and improving efficiency. Telink will continue to provide quick-to-market, performance enhanced, cost efficient solutions to our customers.”
“We believe the RVP is going to open a new era for data computation on MCU.” said Frankwell Lin, President of Andes Technology.“We are gratefully to cooperate with Telink and IAR to build the foundation of the RVP ecosystem for edge AIoT. With Telink TLSR9 and IAR EWRISC-V, developers can easily bring into full play the advantage of RVP. Andes contributed the first version of RVP specification to RISC-V last year, and it is at version 0.8 now. We are looking forward to ratification of RVP standard to enable more and more AIoT market for RISC-V with our partners.”
“We are happy to partner with Andes and Telink to deliver innovative new solutions for IoT developers,” says Kiyofumi Uemura, APAC Director, IAR Systems. “Together we have a lot to offer with regards to performance, and by providing maximized code speed and minimized code size for the TLSR9 series, we will create new possibilities to reduce time to market and ensure high quality applications.”
About Telink Semiconductor
Founded in 2010, Telink Semiconductor is a fabless integrated circuit design company with offices in Shanghai, Shenzhen, Taipei, Santa Clara, and London. Telink is dedicated to the development of highly integrated low-power radio frequency and mixed signal system chips for Internet of Things applications. Telink’s product portfolio is aimed at serving markets ranging from smart lighting to home automation to smart cities and currently includes 2.4GHz RF SoCs for Bluetooth, Zigbee, 6LoWPAN/Thread, and HomeKit. Visit Telink at http://www.telink-semi.com.
About Andes Technology
Fifteen years in business and a founding Premier member of RISC-V International, Andes Technology is a leading supplier of high-performance, low-power 32/64-bit embedded processor IP solutions and a major player in pushing RISC-V into the mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as its base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, dual-issue, and/or multi-core capabilities. Visit Andes at https://www.andestech.com
瑞萨电子采用晶心RISC-V 32位CPU内核开发其首款RISC-V架构ASSP产品
日本东京 – 2020年10月1日 – 全球半导体解决方案供应商瑞萨电子集团(TSE: 6723)今日宣布，与RISC-V架构嵌入式CPU内核及相关SoC开发环境的领先供应商晶心科技启动技术IP合作。瑞萨选择AndesCore™ IP 32位RISC-V CPU内核IP，应用于其全新的专用标准产品中，并将于2021年下半年开始为客户提供样片。
晶心科技总经理林志明表示：「瑞萨作为顶级MCU供应商，已将晶心RISC-V内核设计到其预编程的专用标准产品中，对此我们感到十分荣幸。瑞萨和晶心有着相同的愿景——迎接RISC-V成为片上系统芯片(SoC)主流CPU指令集体系结构(ISA)的时代。双方的合作不仅是晶心的里程碑，更标志着开源RISC-V ISA即将成为主流计算引擎。瑞萨的客户亦将受益于面向21世纪计算需求而构建的现代ISA。」
瑞萨电子执行副总裁、物联网及基础设施事业本部总经理Sailesh Chittipeddi表示：「晶心RISC-V核心IP提供的可扩展性能范围、可选安全功能和定制选项，使瑞萨能够为未来针对特定应用的标准产品提供创新解决方案。帮助为现有或新兴应用寻找经济高效替代途径的客户，从更短的上市时间和更低的开发成本中获益。」
瑞萨基于RISC-V核心架构的预编程ASSP器件，结合专用的用户界面工具来设置应用的可编程参数，将为客户构建完整且优化的解决方案。此功能消除了RISC-V开发初期及软件投资相关的壁垒。此外，瑞萨广泛的区域合作伙伴拥有丰富的专业知识，将为客户提供前沿、专注的技术支持。
关于瑞萨电子集团
瑞萨电子集团 (TSE: 6723) ，提供专业可信的创新嵌入式设计和完整的半导体解决方案，旨在通过使用其产品的数十亿联网智能设备改善人们的工作和生活方式。作为全球领先的微控制器供应商、模拟功率器件和SoC产品的领导者，瑞萨电子为汽车、工业、家居、基础设施及物联网等各种应用提供综合解决方案，期待与您携手共创无限未来。更多信息，敬请访问renesas.com。关注瑞萨电子微信公众号及领英官方账号，发现更多精彩内容。
Andes Technology Steps Up to Premier Membership in RISC-V International; Greatly Expanding its U.S. R&D and Field Application Engineering Staffing
SAN JOSE CA – June 8, 2020 – Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding member of RISC-V International, announces its Premier membership in the organization. Andes President Frankwell Lin takes his seat on the RISC-V International Board. Andes CTO and Executive VP Charlie Su becomes Vice Chair of the RISC-V International Technical Steering Committee. The company will take an active role in the upcoming 2020 RISC-V Summit. Andes’ increased participation in RISC-V International reflects the growing demand for its broad family of RISC-V cores including its highly demanded RISC-V cores with DSP or vector extensions. As a result, Andes Technology is growing its U.S. footprint by expanding its R&D and applications engineering staffing several fold.
“We’ re seeing a rapid expansion in our RISC-V business thanks to system-on-chip designers’ eager adoption of the open source RISC-V CPU instruction set architecture,” said Andes President Frankwell Lin. “Our RISC-V CPU IPs offerings in 2018 have grown three-fold to cover a wide spectrum of applications from IoT devices at the edge to compute intensive servers in the cloud. Last year, our RISC-V solutions have already represented the major share of Andes’ business.”
“The Andes growing R&D team worldwide has demonstrated its engineering ingenuity in our expanding RISC-V offerings,” said Andes Technology CTO and Executive VP Charlie Su. “We developed powerful internal design tools to quickly architect, design, and verify a new processor core. This design flow allows us to rapidly launch a new product to meet rapidly evolving market demand. The development of Andes NX27V RISC-V core with vector extension is a prime example. NX27V is the world first commercial RISC-V vector processor. Andes engineering team had launched and integrated it into customer’s SoC design in a short time. Andes had productized this CPU design automation expertise in the form of our Andes Custom Extension™ (ACE) and COPILOT tool that allows SoC designers to add custom instructions to our RISC-V CPU to make it unique to their solution.”
“Andes USA’s growing footprint has included expanding R&D staffing as well as sales and field application engineering,” said Emerson Hsiao, Andes Technology USA Corp. Senior VP. “In spite of the current constrained business atmosphere, Andes USA continues to experience strong demand for our RISC-V IP solutions. This is in no small part due to Andes’ powerful design automation tools Andes Custom Extension™ and COPILOT. They allow designers to create custom instructions to greatly accelerate performance while drastically reducing power consumption. This capability contributed significantly to the business growth for Andes USA. We continue to look for talented individuals to help us with our growth.”
About Andes Technology Corp.
Andes Technology Corporation is a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment that serves the rapidly growing global market for embedded system applications. As the founding Premier member of RISC-V International, Andes is the first mainstream CPU vendor that adopted the RISC-V as the base of its fifth-generation architecture, the AndeStar™ V5. To meet the demanding requirements of today’s electronic devices, Andes delivers highly configurable and performance-efficient CPU cores. They come with full-featured integrated development environment and comprehensive software/hardware solutions to help designers innovate their SoCs in a shorter time to market. In 2019, the volume of SoCs Embedded with Andes CPUs surpassed the 1.5-billion mark. Andes Technology’s comprehensive RISC-V CPU families range from the entry-level 32-bit N22, mid-range 32-bit N25F/D25F/A25/A27 and 64-bit NX25F/AX25/AX27, to the high-end multicore A(X)25MP and vector processor NX27V. Coming soon is the superscalar 45 series.