AndesCore™ NX25F

Compact High-Speed 64-bit CPU Core

AndesCore™ NX25F Overview

  • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
  • Floating point extension
  • Andes extensions, architected for performance and functionality enhancements
  • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
  • 64-bit CPU architecture, enabling software to utilize the memory spaces far beyond 4G bytes imposed by 32-bit CPUs
  • 16/32-bit mixable instruction format for compacting code density
  • Branch predication to speed up control code
  • Return Address Stack (RAS) to speed up procedure returns
  • Physical Memory Protection (PMP)
  • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
  • Enhancement of vectored interrupt handling for real-time performance
  • Advanced CoDense™ technology to reduce program code size

AndesCore™ NX25F is a compact 64-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is tailored for high-performance embedded applications that needs to access address space over 4GB. NX25F also supports single- and double-precision floating point instructions. NX25F comes with options, including branch prediction for efficient branch execution, Instruction and Data caches, Local Memories for low-latency accesses, ECC for L1 memory soft error protection, and Andes Custom Extension™ (ACE) to add proprietary instructions to accelerate performance/power consumption critical spots.

NX25F's 5-stage pipeline is optimized for high operating frequency and high performance. Features also includes PLIC and vectored interrupts for serving various types of system events, AXI or AHB 64-bit data bus for addressing up to 64-bit address, PowerBrake, QuickNap™ and WFI mode for low power and power management, and JTAG debug interface for development support.

Applications

  • Large-scale network controllers
  • High capacity storage devices
  • Data analytic accelerators
  • Computer Vision and Pattern Recognition
  • Artificial Intelligence to Deep Learning

Block Diagram

Development Tools

  • AndeSight™ Integrated Development Environment
  • COPILOT: Custom-OPtimized Instruction deveLOpment Tool for ACE
  • ICE debugging hardware

Key Features and Performance

AndeStar™ V5 Architecture

Key FeaturesBenefits
RISC-V RV64IMACFD Instructions
  • State-of-the art ISA from latest developments in computer architecture
  • Industry standard and open architecture
64-bit CPU architecture Enabling software to utilize the memory spaces far beyond the 4G byte limit of 32-bit CPUs
RISC-V single and double precision floating point instruction Accelerate the processing of high precision arithmetic
Andes Extended Instructions Andes exclusive performance and functionality enhancements
Andes Custom Extension™ (ACE) option to create customized instructions for software acceleration
  • Add customized instruction extensions to facilitate Domain-Specific Architecture/Acceleration (DSA)
  • Boost application performance significantly, at the same time maintain the programmability
  • Powerful constructs are available to define high level instruction
  • ACE design is based on Verilog and C languages which are familiar to the designers
  • The COPILOT tool automatically generates the extended CPU and software toolchain
  • Do not require expertise in processor pipeline to design ACE instructions
16/32-bit mixable instruction format For compact code density
32 general-purpose registers For better code size and performance
Machine (M) and User (U) Privilege levels Embedded systems with privilege protections

CPU Core

Key FeaturesBenefits
3.22 DMIPS/MHz, 3.52 CoreMark/MHz* Superior performance-per-MHz
5-stage pipeline, with a full-cycle reserved for critical SRAM accesses Superior performance-efficiency, while allowing for high speeds

Extensive branch predication features

  • Branch Target Buffer (BTB): 32, 64, 128 or 256-entry
  • Branch History Table (BHT): 256-entry, with 8-bit branch history
  • Return Address Stack (RAS): 4-entry
  • Branch Target Buffer and Branch History Table to speed up control codes
  • Return Address Stack to speeds up procedure returns
Physical Memory Protection (PMP), 16 regions Basic read/write/execute memory protection with minimum cost
Performance monitors Program code performance tuning
StackSafe™ hardware stack protection
  • Easy identification of stack size threshold during development
  • Hardware error detection of stack overflow and underflow at runtime

Multiplier options

  • Fast multiplier: pipelined, 2-cycle
  • Small multipliers: producing 1, 2, 4, or 8 bits per cycle
Option to choose between speed and area according to application's requirements
PowerBrake technology Performance throttling to digitally reduce power consumption
QuickNap™ technology Fast power-down/wake-up support for caches

* BSP v5.0.0, DMIPS/MHZ without no-inline option, best performances

Memory Subsystems

Key FeaturesBenefits

I-Cache & D-Cache

  • Size: 8KB to 64KB
  • Set associativity: Direct-mapped, 2-way or 4-way
  • Accelerating accesses to slow memories
  • Flexible cache configurations

ILM & DLM

  • Size: 4KB to 16M
  • SRAM or AHB-Lite interface support
  • Bus masters accesses by AHB slave port
  • For deterministic and efficient program execution
  • Flexible size selection to fit diversified needs
Soft-error protection: ECC or parity for I-Cache and D-Cache, ILM and DLM with SRAM interface Code and data integrity protection
Bus master port: AHB or AXI with 64-bit data, 32 to 64-bit address, AXI with I/D separate or joint bus User-selectable bus interface for optimal efficiency
Bus save port: AHB with 64-bit data, for ILM/DLM accesses Efficient data transfer between CPU and SoC masters
Core/bus clock ratio of N:1 Simplified SoC integration

Platform-Level Interrupt Controller (PLIC)

Key FeaturesBenefits

Implements RISC-V PLIC specification

  • Up to 1023 PLIC interrupt sources
  • Up to 255 PLIC interrupt priority levels
  • Up to 16 PLIC interrupt targets
Allow individual interrupts to be serviced and prioritized without sharing

Enhanced interrupt features

  • Vectored interrupt dispatch
  • Priority-based preemption
  • Selectable edge trigger or level trigger
  • Faster interrupt handling for real-time applications
  • Complete hardware preemption support for faster response
  • Flexible interrupt source interface for simpler SoC design

Debug Support

Key FeaturesBenefits
Implements RISC-V debug specifications Supported by industry debug tool suppliers
JTAG Debug Port Industry-standard support
Embedded Debug Module with up to 8 triggers Flexible configurations to tradeoff between gate count and debugging capabilities
Exception redirection support Entering debugger upon selected exceptions without using breakpoints

Performance

Core, ProcessNX25F (w/o FPU), 28HPC+
Frequency (MHz) 50 Area (mm2) 0.043
Dynamic power (uW/MHz) 5.1
Frequency (MHz) 50 Area (mm2) 0.043
Core, ProcessNX25F (w/o FPU), 28HPC+NX25F (with FPU), 28HPC+
Frequency (MHz) 1000 1000
Dynamic power (uW/MHz) 6.0 8.6
Area (mm2) 0.044 0.113

* Base configuration, SVT 9-track library, SS corner, 0.81V, -40°C, and with I/O constraint. Power consumption at TT corner, 0.9V, 25°C 

Product Package

NX25F with CPU Subsystem

  • Pre-integrated NX25F, PLIC, Debug Module and simulation-only encrypted Platform

NX25F with AE350 Platform

 
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