AndesCore™ N7

Entry-level Low-Power 32-bit Processor

AndesCore™ N7 Overview

  • Seamless migration to full 32-bit environment from 8/16-bit MCUs
  • Low power consumption for extended battery life
  • Small footprint with low gate count and high code density
  • Speed-up and power reduction for Flash accesses by FlashFetch technology
The AndesCore™ N7, a family of small cores serves applications including embedded processing devices that require low energy consumption, such as controllers for touch screen, storage, hand-held devices, sensors, and for network connectivity applications like loT (Internet-of-Things).  The N7's ultra-low power consumption and small size was created for performance constrained SOC designs. The N7's features the latest AndeStar™ V3m architecture and a 2-stage pipeline that helps delivering an impressive 168 DMIPS/mW, >40% better than competitive products. Its FlashFetch technology can boosts higher latency flash memory performance without consuming added power. The AndesCore™ N7 can be as small as 12K gates. This makes it an ideal alternative to 8051 and other 8-bit processor cores, while delivering the programmability benefits of a 32-bit processor solution.  

Applications

  • Internet of Things (IOT)
  • Sensor fusion
  • Smart energy monitor and control
  • Home security and remote control
  • Gas/water/electronic metering
  • Medical device
  • Wearable device
  • Education device

Block Diagram

Development Tools

  • AndeSight™ Integrated Development Environment
  • AICE JTAG/SDP debugger hardware

Key Features and Performance

AndeStar™ V3 Architecture

Key FeaturesBenefits
21st-century RISC-like instruction setBetter performance for modern compiler
V3 subset for MCU most frequency used instructionsSmaller die size and lower power consumption
16/32-bit mixable opcode formatSmaller code size
All-C Embedded ProgrammingFaster SW development and easier maintenance
Hardware dividerMore performance
Direct support of up to 32 interrupts with programmable priority levelsQuick identification of interrupt sources and fast assignment of service routines
16MB/4G address spaceLess address bits option leading to small gate count
Memory mapped IOEasy to program and friendly to compiler

CPU Core

Key FeaturesBenefits
1.71 DMIPS/MHz* 3.36 CoreMark/MHz*Superior performance-per-MHz
2-stage pipelineSuperior performance-efficiency, while allowing for high speeds

Choice of multipliers

  • Fast (1 cycle) for performance
  • Small (<0.5K gates) for size
  • More performacne
  • Smaller size
Hardware stack protectionStack size determination and runtime overflow error detection
Processor state busSimplification SoC design and debugging
Performance monitorsProgram code performance tuning

Interface to FlashFetch IP (separately licensable) which contains following options

  • Prefetching functionality
  • Caching functionality
  • SPI interface to external flash
Slow flash memory acceleration and power consumption reduction
Extensive clock gating and logic gatingLower power
N:1 core/bus clock ratiosSimplified SoC integration
Low-latency vectored interruptFaster context switch for real-time applications
Completion of most operations in 1 cycle Single-cycle capable for Local Memory and AHB bus accessesBetter performance-efficiency
PowerBrake technologyPeak power consumption reduction

* BSP v4.2.0, DMIPS/MHZ without no-inline option, best performances

Memory Subsystems

Key FeaturesBenefits

Optional External Instruction and Data Local Memory

  • Size: 0KB to 4MB
  • ILM: program code, data and IO
  • DLM: program data and IO

Higher efficiency for program execution

  • Flexible size selection to fit diversified needs
  • Capable of replacing DLM and bus for lower cost
  • Capable of replacing bus for lower cost
BIU supports AHB-lite or APBUser-selectable bus interface for optimal efficiency

Debug Support

Key FeaturesBenefits
2-wire Serial Debug Port or 5-wire JTAG Debug PortLow-cost 2 wire support and industry-standard 5-wire support

Embedded Debug Module (EDM)

  • Up to 8 breakpoints and watchpoints
  • Secured debug access to system address space
  • Flexible configurations to trade off gate count and debugging capabilities
  • Code and data protection by allowing only authorized debugging

Performance

Process90LP40LP28HPM
Frequency (MHz)505050
Dynamic power (uW/MHz)8.73.92.1
50505050

* Base configuration, Power consumption at typical process corner, Vdd (90LP: 1.2V, 40LP: 1.1V, 28HPM: 0.9V), 25°C

Process40LP28HPM
Frequency (MHz)279506
Dynamic power (uW/MHz)5.93.9
Area (mm2)0.0260.013

* Base configuration, LVT library; Frequency at slow process corner, 40LP:0.99V, 28HPM:0.81V, 125°C and without I/O constraint; Power consumption at typical process corner, Vdd (40LP: 1.1V, 28HPM: 0.9V), 25°C

Close Menu