AndesCore™ is made up of a series of high performance 32-bit/64-bit CPU core families specially designed to target different market segments of today’s emerging embedded applications. AndesCore processors are based on the AndeStar™ V5 Instruction Set Architecture (ISA), which is compliant to the RISC-V technology.
The 5-stage pipeline 25-Series (N(X)25F, D25F, A(X)25, A(X)25MP), 27-Series (A(X)27, A(X)27L2, NX27V), and 8-stage in-order superscalar 45-Series (N(X)45, D45, A(X)45, A(X)45MP) families are based on Andes’ latest AndeStar™ V5 architecture. The 32-bit cores (N25F/D25F/A25/A25MP/A27/A27L2/N45/D45/A45/A45MP) are compliant with RV32IMAC, and the 64-bit cores (NX25F/AX25/AX25MP/AX27/AX27L2/NX45/AX45/AX45MP) with RV64IMAC instruction sets. All of them are equipped with optional single and double precision floating point instruction sets. The A-prefix is Linux capable, and N-prefix supports RTOS, while D-prefix supports RISC-V packed SIMD/DSP instructions (P-extension draft), which is developed by Andes and contributed to the RISC-V foundation.
NX27V is a vector processor with RISC-V V-extension that is welcome by AI/Deep Learning, video and image processing applications. Moreover, PMP (Physical Memory Protection) is available on all V5 cores. A(X)25MP, A(X)27L2 and A(X)45MP deploy L2 cache controller that improve memory transaction efficiency significantly. Furthermore, A(X)25MP and A(X)45MP, supports up to 4 cores with cache coherence, provides more computing power for heavy duty applications . 27 and 45-Series both use “MemBoost” technology to vastly expand the bandwidth of its memory subsystem. Andes extends RISC-V with features including its own instructions to improve performance and functionality, Andes Custom Extension™ (ACE) to create instructions for customized acceleration, half precision floating point load/store instructions to accelerate high precision arithmetic processing, and enhances RISC-V PLIC (Platform-Level Interrupt Controller) with vectored interrupt dispatch and priority-based preemption to speed up interrupt handling.
All cores are available in platform packages of CPU subsystem pre-integrated with bus controller and peripheral components to facilitate SoC designs, and feature such as PowerBrake, QuickNap™, WFI for additional power saving; StackSafe™ for stack overflow/underflow protection; and CoDense™ for additional code density enhancement on top of RISC-V C-extension.
The versatile and rich features of the AndesCore™ families allow flexible SoC customizations based on the application needs in a design to reduce system power/cost or improve platform performance. AndesCore™ products are available in the form of softcore to broadly satisfy the needs of processor cores in all aspects, including business, market, and technology.
With innovative voltage and frequency scaling protocol and low power memory structure, the AndesCore™ CPU families provide high performance and power-efficiency superior to competing 32-bit/64-bit cores on the market. In addition, AndesCore™ CPU families employ various commonly-used low power design techniques to save energy and further allows SoC-level power management to regulate operating voltage and frequency for better energy/performance outcome.