Webinar: 晶心系統控制處理器(SCP)

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Title: Webinar: Andes SCP – System Control Processor
Date: 2016-12-14
Mistakes in hard coded state machines and glue logic require costly and time consuming silicon respins. Andes' System Control Processor (SCP) reduces your SoC design risk and accelerate design schedule.

In this webinar, Dr. Emerson Hsiao, Senior VP of Andes Technology USA, presented how Andes' SCP provides

  • Easy post silicon design changes, such as re-ordering boot sequences
  • Post silicon bug fixing without re-spinning your chip
  • Faster and easier design and verification by using C-code instead of RTL

If you are interested in watching this video, please contact info@andestech.com

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