AndesCore™ N9

Performance-efficient Mid-range 32-bit Processor

AndesCore™ N9 Overview

  • High performance V3 ISA on a compact CPU architecture
  • Superior total performance deliverable
  • Efficient pipeline optimized for Local Memory accesses
  • High configurability including AXI bus support

The AndesCore N9 Family is intended for deeply embedded applications that require optimal interrupt response features, including wireless networking and sensors, microcontrollers, automotive electronics, and industrial control systems. The low-power N9 Family of processors features low gate count, low interrupt latency, and low-cost debug. The processor family provides superior performance and excellent interrupt handling response while meeting the challenges of low dynamic and static power constraints. 

The AndesCore N9 Family of CPU cores implement v3, the AndeStar™ patented 32-bit RISC-style CPU architecture. The designer can configure certain parameters to adjust the CPU’s size, power, and performance. For example, the N9 core can be configured with 16 or 32 general registers, two or three read ports on the register file, one or two write ports, a fast or a small multiplier, a 24-bit or 32-bit address space, and different bus (APB, AHB, AHB-Lite, AXI) interfaces to connect to the rest of the system.

Applications

  • Wireless device
  • Wireless charger
  • Touch screen controller
  • Storage device
  • Industrial control
  • Biometrics device
  • GPS
  • Game console

Block Diagram

Development Tools

  • AndeSight™ Integrated Development Environment
  • AICE JTAG/SDP debugger hardware

Key Features and Performance

AndeStar™ V3 Architecture

Key FeaturesBenefits
21st-century RISC-like instruction setBetter performance for modern compiler
16/32-bit mixable opcode formatSmaller code size
Optional saturation instructionsEfficient voice applications
16 or 32 general-purpose registersTrade-off between core size and performance requirements
All-C Embedded ProgrammingFaster SW development and easier maintenance
Shadow stack pointerEfficiency and protection with a dedicated kernel stack pointer
Aligned and unaligned load/store multiple word instructions and post-increment load/store memory accessesBetter program code size and performance
Direct support of up to 64 interrupts with programmable priority levelsQuick identification of interrupt sources and fast assignment of service routines
4G or 16MB address spaceFull range or less address bits leading to small gate count
Memory mapped IOEasy to program and friendly to compiler

CPU Core

Key FeaturesBenefits
2.21 DMIPS/MHz* 3.59 CoreMark/MHz*Superior performance-per-MHz
5-stage pipelineSuperior performance-efficiency, while allowing for high speeds
Static branch predicationBetter performance for branches
Hardware stack protectionStack size determination and runtime overflow error detection
Processor state busSimplification SoC design and debuggingFast multipliers (1 cycle)More performance
Performance monitorsProgram code performance tuning

Choice of multipliers

  • Fast (1 cycle) for performance
  • Small (<0.5K gates) for size

Application specific configurations

  • More performance
  • Smaller size
Processor state busSimplification SoC design and debuggingFast multipliers (1 cycle)More performance
Extensive clock gating and logic gatingLower power
N:1 core/bus clock ratiosSimplified SoC integration
Low-latency vectored interruptFaster context switch for real-time applications
Completion of most operations in 1 cycle Single-cycle capable for Local Memory and AHB bus accessesBetter performance-efficiency
PowerBrake technologyPeak power consumption reduction

* BSP v4.2.0, DMIPS/MHZ without no-inline option, best performances

Memory Subsystems

Key FeaturesBenefits

Optional External Instruction and Data Local Memory

  • Size: 0KB to 4MB
  • ILM: program code, data and IO
  • DLM: program data
  • Optional two-port D local memory

Higher efficiency for program execution

  • Flexible size selection to fit diversified needs
BIU supports 32-bit AHB/2AHB/AHB-lite/APB/AXIUser-selectable bus interface for optimal efficiency

Debug Support

Key FeaturesBenefits
2-wire Serial Debug Port or 5-wire JTAG Debug PortLow-cost 2 wire support and industry-standard 5-wire support

Embedded Debug Module (EDM)

  • Up to 8 breakpoints and watchpoints
  • Secured debug access to system address space
  • Flexible configurations to trade off gate count and debugging capabilities
  • Code and data protection by allowing only authorized debugging

Performance

Process90LP40LP28HPM
Frequency (MHz)505050
Dynamic power (uW/MHz)25.910.66.2
Area (mm2)0.100.0350.018

* Base configuration, RVT library. ; Power consumption at typical process corner, Vdd (90LP: 1.2V, 40LP:1.1V, 28HPM: 0.9V), 25°C

Process40LP28HPM
Frequency (MHz)632950
Dynamic power (uW/MHz)11.16.8
Area (mm2)0.0620.027

* Base configuration, LVT library; Frequency at slow process corner, 40LP: 0.99V, 28HPM:0.81V, 125°C and without I/O constraint; Power consumption at typical process corner, Vdd (40LP:1.1V, 28HPM: 0.9V), 25°C

Close Menu