AndesCore™ N15/N15F Overview
- Dual-issue pipeline
- Caches for fast code and data accesses
- Local Memories for deterministic code and data accesses
- Built-in IEEE754-compliant FPU coprocessor (N15F)
- Memory Management Unit (MMU) for Linux
- 64-bit AXI4/AHB/AHBx2 bus interface
N15/N15F are dual-issue superscalar AndesCore™ processors capable of delivering performance at 5.41 CoreMark/MHz, the highest among the same level products in the industry. N15/N15F comes with a variety of configuration options, including MMU, cache and local memory. The 64-bit data buses for caches, local memory and the main bus provide the bandwidth needed for instruction fetch and data access. N15F includes a built-in IEEE-754 compliant floating point unit that enhances the floating point processing capability. N15/N15F is designed for diversified performance-driven applications on the embedded Linux, Real-Time OS or bare metal environment.
Applications
- Industrial Automation
- Advanced Motor Control
- Advanced Driver Assistance System (ADAS)
- Global Position System (GPS)
- Unmanned Aerial Vehicle (UAV)
- Sensor Device/Sensor Hub
Block Diagram
Development Tools
- AndeSight™ Integrated Development Environment
- AICE JTAG/SDP debugger hardware
Key Features and Performance
AndeStar™ V3 Architecture
| Key Features | Benefits |
|---|---|
| 21st-century RISC-like instruction set | Better performance for modern compiler |
| 16/32-bit mixable opcode format | Smaller code size |
| 32 general-purpose registers | Trade-off between core size and performance requirements |
| All-C Embedded Programming | Faster SW development and easier maintenance |
| Shadow stack pointer | Efficiency and protection with a dedicated kernel stack pointer |
| Radix-4 hardware divider | More performance |
| Aligned and unaligned load/store multiple word instructions and post-increment load/store memory accesses | Better program code size and performance |
| 64-bit load/store unit | More performance |
| Direct support of up to 32 interrupts with programmable priority levels | Quick identification of interrupt sources and fast assignment of service routines |
| 4G address space | Full range address space |
| Memory mapped IO | Easy to program and friendly to compiler |
CPU Core
| Key Features | Benefits |
|---|---|
| 3.36 DMIPS/MHz* 5.41 CoreMark/MHz* | Superior performance-per-MHz |
| 6-stage dual-issue pipeline | Capable of processing two instructions in parallel to accelerate performance |
| Extensive branch predication (BTB and RAS) | Better performance for branches |
| Hardware stack protection | Stack size determination and runtime overflow error detection |
| Processor state bus | Simplification SoC design and debugging |
| Performance monitors | Program code performance tuning |
Memory Management Unit
|
|
Memory Protection Unit
| Basic read/write/execute memory protection with minimun cost |
| Fast multipliers (1 cycle) | More performance |
| Extensive clock gating and logic gating | Lower power |
| N:1 core/bus clock ratios | Simplified SoC integration |
| Low-latency vectored interrupt | Faster context switch for real-time applications |
| Completion of most operations in 1 cycle Single-cycle capable for Local Memory and AHB bus accesses | Better performance-efficiency |
| PowerBrake technology | Peak power consumption reduction |
| QuickNap™ automatic state management for fast power-off and wakeup | Better power management efficiency |
Floating point unit (D15F)
| For floating point application |
*BSP v4.2.0, DMIPS/MHZ without no-inline option, best performances
Memory Subsystems
| Key Features | Benefits |
|---|---|
I & D Cache
| Higher performance for large program size
|
Optional External Instruction and Data Local Memory
| Higher efficiency for program execution
|
| ECC or Parity for soft-error protection (Parity protection is valid for D-Cache and DLM only) | Code and data integrity protection |
| Optional 1D/2D DMA with 64-bit transfer | Efficient data transfer |
| BIU supports 64-bit AXI4/AHB/AHB2 | User-selectable bus interface for optimal efficiency |
Debug Support
| Key Features | Benefits |
|---|---|
| 5-wire JTAG Debug Port/Andes 2-wire Debug Port | Industry-standard 5-wire support and Low-cost 2 wire support |
Embedded Debug Module (EDM)
|
|
| Trace interface to the Andes Trace Module (licensed separately) for enabling the tracing capability | Advanced debugging |
Performance
| Process | 28HPM |
|---|---|
| Frequency (MHz) | 50 |
| Dynamic power (uW/MHz) | 17.5 |
| Area (mm2) | 0.050 |
* Base configuration, RVt library. Power consumption at typical process corner, 0.9V, 25°C
| Process | 28HPM |
|---|---|
| Frequency (MHz) | 870 |
| Dynamic power (uW/MHz) | 10.5 |
| Area (mm2) | 0.08 |
* Base configuration, LVt library; Frequency at slow process corner, 0.81V, 125°C and without I/O constraint; Power consumption at typical process corner, 0.9V, 25°C
