2018 Andes RISC-V CON

Nov 13, 2018 (Tue.) 9:00-17:00


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Check out the Agenda.

AGENDA

ABOUT ANDES RISC-V CON

RISC-V, an open instruction set architecture (ISA), has gained momentum and rapidly evolved into a new mainstream embedded processor technology with a rich ecosystem and a fast-growing number of real-world implementations.

In order to foster stronger collaboration on RISC-V across the semiconductor industry, Andes RISC-V CON will focus on this disruptive technology, demonstrating its benefits and identifying commercial strategies.

Andes positions itself as an professional and reliable vendor of RISC-V processors and solutions. It has launched several new RISC-V based products recently.

By bringing together industry experts, the goal is to make it easier for other industry players to quickly bring innovative designs based on the open RISC-V ISA to market.

Venue

Silicon Valley

Nov 13, 2018 (Tue.) 9:00-17:00

Hyatt Regency Santa Clara
5101 Great America Parkway
Santa Clara, California, USA

Contact Us

Main Office
Andes Technology Corporation
10F., No.1, Sec. 3, Gongdao 5th Rd., East Dist., Hsinchu City 30069, Taiwan R.O.C.
TEL:+886-3-5726533
Email
marcom@andestech.com