2018 Andes RISC-V CON

RISC-V from MediaTek’s Perspective

MediaTek
Shichin Ouyang, Director of Technology

Shichin Ouyang received his B.S. from National TsingHua University, Taiwan, and his M.S. from Stanford University, CA, both in Electrical Engineering. He has been working with MediaTek Inc since 2008, where he is currently a Director of Technology on MediaTek's CPU organization. Before joining MediaTek, he was with SUN Microsystems from 1999 to 2008 as a timing lead and a digital circuit designer on multiple Ultra-Sparc processors. At MediaTek, his division’s current focus is on design and implementation of processor subsystems to achieve high performance and low power goals for mobile AP and modem processors.
The speech will give an overview on Mediatek and RISC-V, followed by many common goals that Mediatek and RISC-V share. The focus of speech will be on the potential benefits of RISC-V, and Mediatek’s expectation on RISC-V and its Ecosystems, from a leading fabless IC design company’s perspective.

Comprehensive RISC-V Solutions for Diversified SoCs

Andes Technology
Charlie Su, CTO & Senior VP

Dr. Charlie Su is the first employee of Andes. He is in charge of product development and technical marketing. He spent over 12 years in the Silicon Valley with various technical and management positions at Sun Microsystems, Afara Websystems, C-Cube Microsystems, SGI/MIPS, and Intergraph. He made key contributions to several successful processors such as the Sun multi-core multi-threading Ultrasparc T1 and T2 processors, the C-Cube high-performance E-series MPEG media processors, the MIPS out-of-order R10K processor, and the Intergraph Clipper VLIW processor. Prior to starting Andes, he led the CPU and DSP development in Faraday Technology as Chief Architect.

Unleashing Chip Design Barrier With RISC-V

Andes Technology
Frankwell Lin, President

President Lin started his career being as application engineer in United Microelectronics Corporation (UMC) while UMC was an IDM with its own chip products, he experienced engineering, product planning, sales, and marketing jobs with various product lines in UMC.
In 1995, after four years working on CPU chip product line as business director, he was transferred to UMC-Europe branch office to be its GM when UMC reshaped to do wafer foundry service, he lead UMC-Europe to migrate itself from selling IDM products to selling wafer foundry service.

In 1998, after 14 years working in UMC, President Lin switched job to work in Faraday Technology Corporation (Faraday), he lead ASIC business development as starting, then on-and-off leading ASIC implementation, chip backend service, IP business development, industry relationship development (IR), as well as Faraday's spokesperson, in 2004, he started to lead the CPU project spin off operation of Faraday.

President Lin became co-founder of Andes Technology Corporation (Andes) in 2005 and formally took position to be Andes' President since 2006.

Panel: Is RISC-V Ready for Your Design?

Moderator:
Linley Gwennap , President, The Linley Group
Panelist:
Charlie Su, CTO & Senior VP, Andes
Scott Casper, Director of Sales, America, GOWIN
Larry Lapides, Vice President Sales, Imperas

Scott Casper, Director of Sales, America, GOWIN
Scott Casper brings with him more than 20 years of sales, business development, and general management experience in the semiconductor industry. At GOWIN, Mr. Casper heads up sales, sales operations, and business development activities for the Americas Region, leading the company’s efforts to grow the region in the consumer, communications, automotive, and industrial market segments.

RISC-V Microprocessor Implementation for FPGA Solutions

GOWIN Semiconductor
Jim Gao, Director of Solution Development

Jim Gao – Mr. Gao is Director of Solution Development at GOWIN Semiconductor Corporation since 2016. He leads & coordinates FPGA IP development and project management. Mr. Gao is a technologist with over 25 years of industry professional experience in semiconductor (FPGA/ASIC SoC), electronic design automation, communication, and multimedia consumer electronics . Mr. Gao has held senior management positions and several key design & application lead roles for world-class FPGA/ASIC, System-On-Chip, and IP/IC design companies. Mr. Gao received his Masters of Electrical & Computer Engineering Degree (1993) & Masters of Business Administration Degree (2000) from Portland State University, Oregon, USA.

▸ What’s the speech about?
How to implement the Andes N25 RISC-V core on GOWIN’s GW2A family of FPGA products

Ecosystem and Solutions for AIoT

Andes Technology
Emerson Hsiao, Senior VP

Dr. Hsiao has an extensive background in the ASIC and IP industry. Prior to joining Andes, he worked at Kilopass Technology as the VP of Marketing.
Dr. Hsiao previously held the General Manager position for Faraday Technology USA, where he spent several years in field application in various locations including Taiwan, Japan and USA. Dr. Hsiao worked at UC Santa Barbara as a visiting scholar prior to Faraday.

Thoughts on Hierarchical SoC Verification

XtremeEDA
Jeremy Ralph, Principal Verification Consultant

Jeremy Ralph has 20 years of engineering experience in chip design, verification, firmware, and software development. As a verification consultant with XtremeEDA, Jeremy has launched the riscv-vip open source project, a SystemVerilog project to support pre- silicon verification and debug of RISC-V-based systems.

Prior to joining XtremeEDA, Jeremy played a key role in verifying new PCIe NVMe-based SSD controller chips as part of Intel's Non-Volatile Solutions Group (NSG) where he led verification teams for multiple controllers and served as the verification methodology group leader for all internal SSD controller development.

Earlier in his career, Jeremy founded and led PDTi, a startup that developed and licensed SpectaReg, a web application for automating hardware/software register interface specification management and code-generation.

▸ What’s the speech about?
The talk will discuss hierarchical SoC verification using a constrained-random, coverage-driven methodology with SystemVerilog and UVM. Considerations regarding planning, block-level verification, subsystem verification, and full SoC verification will be discussed. The riscv-vip open source project will also be briefly introduced.

Faraday and RISC-V SoC Based Solution

Faraday
Efren Brito, Field Application and Marketing at Faraday

Efren has over 17 years of experience in the Semiconductor industry focused on ASIC design, technical program management, customer facing application engineering, and ASIC solution sales. He currently serves as Field Application and Marketing Manager at Faraday with a strong foresightedness perspective resulting from a solid ASIC design, field engineering, and sales foundation.

Before joining Faraday, Efren was an AE at Altera specializing in FPGA debug and enablement. Efren was also a SRAM designer, circuit designer, IO characterization engineer, AE, and FAE at IBM.

Efren earned his Master of Science in Electrical Engineering degree from both the Universidad de las Americas in Puebla, Mx. as well as Texas Tech University specializing in pulsed power.

▸ What’s the speech about?
The talk will discuss hierarchical SoC verification using a constrained-random, coverage-driven methodology with SystemVerilog and UVM. Considerations regarding planning, block-level verification, subsystem verification, and full SoC verification will be discussed. The riscv-vip open source project will also be briefly introduced.

Trusted Execution Environments on RISC-V

Hex Five Security
Cesare Garlati, Co-founder

Cesare Garlati is an internationally renowned expert in information security. Former Vice President of mobile security at Trend Micro, Cesare currently serves as Chief Security Strategist at prpl Foundation – a technology nonprofit dedicated to enabling security and interoperability of embedded systems. Cesare is a long- time supporter of the RISC-V Foundation, a key member of the RISC-V security group and co-founder of Hex Five Security – the creator of the first trusted execution environment for RISC-V.

▸ What’s the speech about?
Implementation of Hex Five’s TEE on the N25 RISC-V core.

Cycle Approximate Timing Simulation of Andes RISCV Processors

Imperas Software Ltd.
Larry Lapides, Vice President Sales

Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company.
Before Verisity and SureFire (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in- Residence at Clark University's Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley.

▸ What’s the speech about?
Historically, architectural estimation, analysis and optimization has been done using either manual spreadsheets, hardware emulators, FPGA prototypes, cycle approximate simulators or cycle accurate simulators. These all have significant drawbacks: insufficient accuracy, high cost, RTL availability (meaning that the technique is only available later in the project when the RTL design is complete), low performance.

Instruction accurate software simulation, or virtual platforms, have the speed necessary to cover the range of system scenarios, can be available much earlier in the project, and are typically 5x less expensive than cycle approximate or cycle accurate simulators.

Previously, because of a lack of timing information in the models and simulator, virtual platforms could not be used for timing estimation. We report here on a technique for dynamically annotating timing information to the software simulation results. This has achieved accuracy of better than +/-15%, which is normally good enough for most architectural exploration and system analysis.

In the Open Virtual Platforms (OVP) processor model architecture it is possible to create a standalone library module with entry points that are called when instructions are executed. This library can introspect the running system and calculate an estimate for the cycles taken to execute the current instruction. Not only can these add-on libraries dynamically inspect the running system estimate timing affects, they can annotate calculated instruction cycle timing back into the simulation and affect timing of the simulation.