2018 Andes RISC-V CON

ABOUT ANDES RISC-V CON

RISC-V, an open instruction set architecture (ISA), has gained momentum and rapidly evolved into a new mainstream embedded processor technology with a rich ecosystem and a fast-growing number of real-world implementations.

In order to foster stronger collaboration on RISC-V across the semiconductor industry, Andes RISC-V CON will focus on this disruptive technology, demonstrating its benefits and identifying commercial strategies.

Andes positions itself as an professional and reliable vendor of RISC-V processors and solutions. It has launched several new RISC-V based products recently.

By bringing together industry experts, the goal is to make it easier for other industry players to quickly bring innovative designs based on the open RISC-V ISA to market.

REGISTER

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． 100 loyal and lucky attendees checking in at the event can get a free set of 【RISC-V SDKs】. (List price: US$150. Each SDK comprises a Gowin board with GW2A-18 FPGA containing Andes RISC-V core and Andes AICE-MINI+ linking USB to JTAG for software debug.)
1. Attendees must pre-register online and attend the entire event to get the RISC-V SDKs. There will be a Lucky Draw at the end of the event to make the 100 loyal and lucky attendees’ list available. 2. The giveaway doesn’t apply to attendees registering on site on the day of the event. ． Andes Technology reserves the right to verify all registrations.
． Andes Technology reserves the right to make changes to the program without prior notice.