2018 Andes RISC-V CON

Time Topic Speaker
08:30-09:00 Registration
09:00-09:05 Opening
Frankwell Lin, President
Andes Technology
09:05-09:35 Roadmap Directions for the RISC-V Architecture
Linley Gwennap, Principal Analyst
The Linley Group
09:35-10:05 RISC-V from MediaTek’s Perspective Shichin Ouyang, Director of Technology
MediaTek
10:05-10:45 Comprehensive RISC-V Solutions for Diversified SoCs Charlie Su, CTO & Senior VP
Andes Technology
10:45-11:00 Tea Break
11:00-11:45 Panel: Is RISC-V Ready for Your Design?
Moderator:
Linley Gwennap, President, The Linley Group

Panelist:
Charlie Su, CTO & Senior VP, Andes
Scott Casper, Director of Sales, America, GOWIN
Cesare Garlati, Co-Founder, Hex Five Security
Larry Lapides, Vice President Sales, Imperas
11:45-12:10 Unleashing Chip Design Barrier with RISC-V Frankwell Lin, President
Andes Technology
12:10-12:30 Gowin FPGA for RISC-V Solution Jim Gao, Director of Solution Development
GOWIN Semiconductor
12:30-13:30 Lunch
13:30-14:00 Ecosystem and Solutions for AIoT Emerson Hsiao, Senior VP
Andes Technology
14:00-14:30 RISC-V SoC Hierarchical Verification Jeremy Ralph, Principal Verification Consultant
XtremeEDA
14:30-15:00 Faraday and RISC-V SoC Based Solution Efren Brito, Senior FAE Manager
Faraday
15:00-15:40 Tea Break
15:40-16:10 Making RISC-V the Most Secure Platform Ever Cesare Garlati, Co-founder
Hex Five Security, Inc.
16:10-16:40 Cycle Approximate Timing Simulation of Andes RISC-V Processors Larry Lapides, Vice President Sales,
Imperas Software
16:40-17:10 Andes SW Solutions for RISC-V Justin Tseng,
VP of RD-VLSI and M&S Andes Technology
17:10- Q&A