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Read more about the article HighTec C/C++ Compiler Suite Supports Andes’ ISO 26262 Certified RISC-V IP for Automotive Safety and Security Applications

HighTec C/C++ Compiler Suite Supports Andes’ ISO 26262 Certified RISC-V IP for Automotive Safety and Security Applications

Saarbrücken/Germany — Nov 28, 2024 — HighTec EDV-Systeme GmbH, a leading provider of automotive compiler solutions, has announced support for Andes’ RISC-V IP in its highly optimized C/C++ compiler for the automotive market. This support marks a milestone for automotive software developers, as HighTec’s compiler now seamlessly supports the Andes’ functional safety certified RISC-V cores to ensure optimized code generation for automotive processors, improving efficiency and performance.

Andes is committed to providing state-of-the-art automotive solutions with ISO 26262 compliant AndesCore™ RISC-V IP, software, and development tools.  In 2022, Andes launched the industry’s first certified ASIL-B RISC-V CPU IP with full compliance, the N25F-SE. Building on this achievement, Andes has expanded its Safety Enhanced (SE) series to include the DSP-capable ASIL-B D25F-SE, the streamlined and secure ASIL-D D23-SE, the high-performance ASIL-D D45-SE, and the upcoming 60-SE series targeting ADAS and IVI applications.  With certified RISC-V IP and a robust ecosystem of ISO 26262 qualified tools and software, Andes enables customers to achieve ISO 26262 certification with their end-products. The SE cores offer flexibility, scalability, security, and superior performance to meet the diverse needs of modern automotive applications.

The HighTec C/C++ compiler is built on the modern LLVM (Low Level Virtual Machine) open-source technology, and ensures optimal utilization of Andes RISC-V IP performance, enabling automotive software developers to achieve faster and more efficient code execution. Known for its fast build times, HighTec’s compiler generates highly dense and reliable code. Developers particularly value the Clang front-end for its extensive analysis options. Qualified up to ASIL D – the highest level of functional safety – HighTec’s C/C++ compiler includes a qualification toolkit that simplifies the development and certification of safety-critical applications, helping automotive software developers accelerate the certification process.

“HighTec has been committed to advancing the automotive industry for more than 20 years and is one of the world’s first ASIL certified compiler suppliers. We are pleased to add HighTec to Andes’ automotive ecosystem,” said Dr. Charlie Su, President and CTO of Andes Technology. “This latest C/C++ compiler brings significant value to our customers, offering them a differentiated, ISO 26262 certified RISC-V development environment that enhances code efficiency and performance.”

Mario Cupelli, CTO at HighTec, said, “Andes delivers the leading portfolio of ISO 26262 fully compliant RISC-V IPs, and we are excited to join their ecosystem. HighTec’s automotive compiler will provide full commitment to Andes RISC-V IP lifecycle support. Automotive customers can fast-track compliance efforts and improve the performance and robustness in safety-critical RISC-V applications, accelerating time to market for RISC-V-based automotive software solutions.”


About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion.
For more information, please visit https://www.andestech.com/en/homepage. Follow Andes on Twitter, LinkedIn, YouTube and Facebook.

 

About HighTec EDV Systeme GmbH

HighTec EDV-Systeme GmbH, Saarbruecken/Germany, is the world’s largest commercial provider of compilers using innovative open-source technologies and offers ISO 26262 ASIL D certified tools for embedded software development, the real-time operating system PXROS-HR, and a wide range of design-in services.

HighTec’s ASIL D qualified C/C++ compiler for leading multicore microcontrollers in the automotive and industrial sectors such as Arm®, TriCore™/AURIX™/TRAVEO™ families, RISC-V, Power Architecture (PowerPC) and GTM architectures are continuously adapted and optimized to new architectures in close cooperation with the silicon partners.

In addition to the multi-architecture compiler, HighTec offers PXROS-HR, a safety-certified multicore RTOS for applications with safety and multicore requirements. PXROS-HR guarantees robustness, safety, high performance, and data security in real-time environments. PXROS-HR is certified according to ISO 26262 ASIL D / IEC 61508 SIL 3 and is complemented for ASIL D development by a Tool Qualification Kit as a basis for the certification of customer applications.

Complementing this portfolio, HighTec offers development, training and consulting services.

Founded in 1982, HighTec is a privately held global company with offices in Germany, the Czech Republic, the Netherlands, Hungary and China. For more information about HighTec EDV-Systeme GmbH, visit www.hightec-rt.com.

Company Contact

HighTec EDV-Systeme GmbH

Europaallee 19

66113 Saarbrücken/Germany

Tel.: +49 681 92613-16

Email: info@hightec-rt.com

Press Contact Agency

Catherine Schneider

Mexperts AG

Tel.: +49 8143 59744-27

Email: catherine.schneider@mexperts.de
Continue ReadingHighTec C/C++ Compiler Suite Supports Andes’ ISO 26262 Certified RISC-V IP for Automotive Safety and Security Applications
Read more about the article Andes Technology Collaborates with Lauterbach to Deliver RISC-V Trace Solution

Andes Technology Collaborates with Lauterbach to Deliver RISC-V Trace Solution

HSINCHU, TAIWAN — Nov 26, 2024 — Lauterbach, the leading provider of development tools for embedded systems, and Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of RISC-V processor IP, today proudly announce their collaboration that enhances the debugging and tracing experience for engineers using Andes’ advanced NCETRACE200 trace IP with Lauterbach’s industry leading development tools TRACE32®.

With the growing demand for RISC-V architectures in various applications, the combination of Lauterbach’s TRACE32® tools and Andes’ NCETRACE200 trace solution empowers developers to have deep, non-intrusive trace visibility into their System-on-Chip (SoC) to assist debug & trace, accelerate time-to-market and achieve higher levels of reliability, performance and efficiency in their embedded products.

AndesCore™ NCETRACE200 subsystem is a non-intrusive tracing solution designed for the Andes RISC-V processor portfolio that spans from small, low-power MCUs to high-performance OoO application processors.  Key features include:

  • RISC-V N-Trace compatible trace encoder, timestamp generator and decoder
  • Multi-core tracing, up to 8 RISC-V harts
  • Configurable size Trace Buffer
  • Mixed-ISA environment supported, including compatibility with the CoreSight™ technology by Arm®.
*ARM® and CoreSight™ are trademarks or registered trademarks of ARM Limited in the United States and other countries

“We are excited to support Andes Technology trace solution with our TRACE32® tools,” said Norbert Weiss, Managing Director at Lauterbach. “Our collaboration will provide engineers with the tools they need to maximize the potential of their RISC-V designs, fostering innovation and efficiency in embedded systems.” Andes also expressed enthusiasm about the partnership. “Lauterbach is our long-term partner for many years. Working with Lauterbach allows us to deliver a comprehensive debug and trace experience to our customers, further solidifying our position in the embedded systems market,” said Dr. Charlie Su, president and CTO at Andes Technology. “This collaboration will pave the way for innovative developments in the RISC-V landscape, supporting a new generation of embedded solutions.”

 

About Lauterbach
Lauterbach is the leading manufacturer of cutting-edge development tools for embedded systems with more than 45 years of experience, serving customers all over the world and partnering with all semiconductor manufacturers. The company has played a key role in the RISC-V Foundation working groups that have defined debug and trace standards for RISC-V-based CPUs.
For more information, please visit https://www.lauterbach.com. Follow Lauterbach on LinkedIn and YouTube.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion.
For more information, please visit https://www.andestech.com/en/homepage. Follow Andes on Twitter, LinkedIn, YouTube and Facebook.

Continue ReadingAndes Technology Collaborates with Lauterbach to Deliver RISC-V Trace Solution
Read more about the article Fractile Licenses Andes Technology’s RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference

Fractile Licenses Andes Technology’s RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference

San Jose, CA — Oct. 22, 2024 — Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, are proud to announce a partnership with Fractile, the company building the chips and systems needed to reach the next frontier of AI performance. Fractile is developing AI inference accelerators based on in-memory compute, and aim to be able to run frontier AI models – large language, vision and audio models – two orders of magnitude faster than existing hardware, at a tenfold reduction in cost.

Large language models and other foundation models have become the driving force behind the skyrocketing scale of data center AI compute requirements. From ChatGPT to the open-source Llama model series, LLMs and other foundation models are finding widespread application. Model inference – the process of serving these trained models –  is coming to be the dominant portion of compute costs, exceeding the cost of model training.  Fractile has licensed the powerful Andes AX45MPV RISC-V vector processor, combined with ACE (Andes Automated Custom Extension™) and Andes Domain Library, and plans to incorporate the vector processing unit into their first generation data center AI inference accelerator.

Fractile’s uses novel circuits to execute 99.99% of the operations needed to run model inference in on-chip memory. This removes the need to shuttle model parameters to and from processor chips, instead baking computational operations into memory directly.  This architecture drives both much higher energy efficiency (TOPS/W) as well as dramatically improved latency on inference tasks (tokens per second per user in an LLM context, for instance). The company has been betting on inference scaling – leveraging more inference time-compute to improve AI performance – as the next frontier of AI scaling. The AI world seems to agree, with OpenAI recently releasing their latest LLM, o1, which requires orders of magnitude more inference compute than previous LLMs. Fractile’s hardware and software stack is built to take models that can still take many seconds to produce an answer on current hardware, and make this instantaneous.

As part of the collaboration, Fractile will integrate Andes Technology’s high-performance RISC-V vector processor with its own groundbreaking in-memory computing architecture via ACE. Fractile’s architecture leverages the strengths of both companies, aiming to deliver an exceptionally fast and cost-effective AI inference system that overcomes the limitations of conventional computing methods – blasting through the memory bottleneck.

Dr. Charlie Su, President and CTO of Andes Technology, expressed his enthusiasm for the partnership, “AX45MPV, with strong compute capabilities, high memory bandwidth and the flexible ACE tool, has been chosen by innovative AI companies large and small since its debut in 2023. Andes RISC-V vector processors have enabled many AI SoCs to break free from architecture limitation and achieve new levels of performance and efficiency. We are confident that the synergy between Fractile’s In-Memory Computing technologies and Andes’ award-winning RISC-V vector processing will lead to yet another success.”

Dr. Walter Goodwin, CEO and founder of Fractile, added: “The limitations of existing hardware present the biggest barrier to AI performance and adoption. Andes Technology has unmatched technical and commercial leadership on RISC-V vector processors and is a natural partner for us as we build Fractile’s accelerator systems. Building hardware for AI acceleration is intrinsically hard – the world’s leading models can change overnight, while chips take time to bring to market. Software-programmable vector processors like Andes’ are a key part of staying robust to these changes. We’re delighted to announce this collaboration as Fractile furthers its mission to supercharge inference.

For more information about Andes Technology and Fractile, please visit their respective websites at www.andestech.com and www.fractile.ai.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! ! 

About Fractile
Fractile is an AI hardware company that is building its first groundbreaking new AI chip, capable of running state-of-the-art AI models up to 100x faster and 10x cheaper than existing hardware. Founded in 2022 in London by 28-year-old artificial intelligence PhD Walter Goodwin, Fractile’s transformative computing technology will enhance collective AI capabilities by enabling the largest and most capable neural networks of today and tomorrow to run faster, more efficiently and more sustainably. The company has raised $17.5m (£14m) in funding from investors including the NATO Innovation Fund, Kindred Capital, Oxford Science Enterprises, Cocoa and Inovia Capital, as well as angel investors including Hermann Hauser (founder, Acorn, Amadeus), Stan Boland (ex-Acorn, Icera, NVIDIA and Five AI) and Amar Shah (co-founder, Wayve).

Continue ReadingFractile Licenses Andes Technology’s RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference
Read more about the article Andes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification

Andes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification

Hsinchu, Taiwan  – Oct 22, 2024  – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, proudly announces the launch of its industry-leading functional safety RISC-V processor AndesCore™ D45-SE, targeting ISO 26262 ASIL-D (Automotive Safety Integrity Level D) certification.

The D45-SE, derived from the production-proven D45, is a 32-bit, 8-stage dual-issue processor that supports the RISC-V GCBP extensions, including single/double precision FPU, 16-bit compression, bit manipulation, draft of packed SIMD/DSP extensions, and the Andes performance enhancements. Furthermore, it incorporates numerous safety features, such as dual-core lockstep (DCLS), a real-time diagnostic safety circuit that utilizes an additional processor and a set of comparators to enhance the diagnostic coverage; ECC for memory soft error protection; bus protection to secure bus transactions; a core trap status bus interface that provides real-time trap status information from the core; and StakSafe™, a hardware mechanism that  protects the stack, and maintains the same outstanding 6.12 Coremark/MHz as the D45. With these safety enhancements, the D45-SE ensures fault tolerance that meets the rigorous demands of safety-critical applications.

Additionally, it supports split-mode, allowing two cores to run independently when split-lock is configured. The processor also offers comprehensive safety documentation and support to facilitate ISO 26262 compliance, assisting customers in integrating safety features into their designs. The D45-SE marks a milestone, underscoring Andes’ commitment to providing industry -leading, mission-critical solutions for the automotive industry and beyond.

“We are thrilled to announce the D45-SE, a high-performance RISC-V processor engineered to deliver exceptional safety and reliability. It is a testament to our dedication to delivering safe and reliable solutions,” said Frankwell Lin, Andes Chairman and CEO. “This accomplishment reflects our ongoing commitment to supporting the automotive industry’s drive towards higher safety standards and innovation.”

 About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion.For more information, please visit https://www.andestech.com/en/homepage  Follow Andes on Twitter, LinkedIn, YouTube and Facebook.

Continue ReadingAndes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification
Read more about the article DeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop

DeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop

San Jose, CA — Oct 22, 2024 — DeepComputing, a pioneer in RISC-V innovation, today announced a strategic partnership with Andes Technology Corporation, a leading provider of high-efficiency, low-power 32/64-bit RISC-V processor cores. Together, the two companies collaborate to develop the world’s first RISC-V AI PC, powered by Andes’ 7nm QiLai SoC. This innovated low-power PC will come equipped with Ubuntu Desktop and aims to redefine AI computing by combining industry-leading hardware and software designed specifically for RISC-V.

The collaboration marks a significant milestone in the evolution of AI PCs, which utilize artificial intelligence to enhance productivity, creativity, entertainment, security, and more. The power-efficient RISC-V AI PC, based on the QiLai SoC, integrates a multi-core CPU, vector processor, GPU, and various peripherals for optimal performance, and AI workload handling. This product is designed to cater to developers and enterprises looking for advanced, open-standard RISC-V solutions.

Revolutionizing AI Computing with RISC-V and Andes Technology

The Andes QiLai SoC contains 2 Andes RISC-V processors: a high-performance quad-core  AX45MP cluster and an NX27V vector processor. The AX45MP superscalar multicore is optimized for Linux-based applications by configuring a 2MB Level-2 cache and a Memory Management Unit (MMU). The NX27V vector processor, with a 512-bit vector length and data path width, is specifically designed to handle AI workloads efficiently. Running at up to 2.2 GHz (AX45MP) and 1.5 GHz (NX27V), the QiLai SoC delivers high performance while maintaining low power consumption of approximately 5W at full speed. A configuration of the AX45MP is used in the Renesas RZ/Five MPU while two instances of the NX27V help construct the PE’s (Processing Elements) in the 8×8 PE array of the Meta Training and Inference Accelerator (MTIA).

“We are excited to work with DeepComputing and Canonical for this AI PC project based on our newly-introduced QiLai SoC.” said Frankwell Lin, Chairman and CEO of Andes. “The QiLai leverages TSMC’s 7nm process technology and underscores our commitment to supporting the expansion of the RISC-V ecosystem. As always, Andes continues its position as a pure-play IP provider, not entering the chip business. Andes welcome chip company considering to license QiLai as an SoC IP for production. This AI PC project will demonstrate the power of the RISC-V architecture for general application processing and AI acceleration, and provide a powerful RISC-V platform for application development and processor IP evaluation.”

The World’s First RISC-V AI PC

The RISC-V AI PC developed by DeepComputing and Andes will feature Ubuntu Desktop. In addition, there are a suite of tools and frameworks optimized for AI workloads, including the AndeSight™ toolchains, AndeSoft™ software stacks, and AndesAIRE™ NN SDK, which compiles AI/ML models to executables running on the NX27V vector processor.

The product represents a breakthrough in AI PC design, offering an open and modular approach that caters to the growing RISC-V developer community. Designed for a wide range of use cases, the RISC-V AI PC supports diverse AI-driven applications, from productivity and creativity to gaming and security.

Gordan Markuš, Director of Silicon Alliances at Canonical noted, “We are thrilled to collaborate with DeepComputing and Andes on this groundbreaking project. By equipping the world’s first RISC-V AI PC with Ubuntu Desktop, we’re not only offering a powerful development platform but also enabling a robust, open-source software ecosystem. This partnership will help accelerate the adoption of RISC-V technology and broaden the possibilities for developers and businesses working with AI at the edge.”

Expanding the RISC-V Ecosystem

By offering the world’s first RISC-V AI PC, DeepComputing and Andes aim to accelerate the development of RISC-V-based AI solutions and expand the reach of RISC-V in the broader computing landscape. This collaboration is driven by the growing demand for RISC-V platforms that enable fast software development, evaluation, and deployment.

“We’re excited to partner with Andes Technology on this innovative project,” said Yuning, CEO of DeepComputing. “This partnership aligns with our mission to push the boundaries of RISC-V technologies and provide developers with the tools and platforms they need to shape the future of AI computing.”

The RISC-V AI PC platform will be unveiled at the RISC-V Summit NA 2024, where it will be showcased at the DeepComputing booth. The product will be officially available in early 2025.

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn、Facebook、X、Bilibili  and YouTube! 

About Canonical

Canonical, the publisher of Ubuntu, provides open source security, support and services. Their portfolio covers critical systems, from the smallest devices to the largest clouds, from the kernel to containers, from databases to AI. With customers that include top tech brands, emerging startups, governments and home users, Canonical delivers trusted open source for everyone. Learn more at https://canonical.com/.

About DeepComputing

Formed in 2022 by a group of dedicated RISC-V enthusiasts, DeepComputing is a pioneer in RISC-V innovation, leading the way in connecting developer communities, suppliers, tools and systems with the world of RISC-V. We are committed to advancing the adoption and implementation of RISC-V beyond existing ISA chipsets. Together with a diverse and dedicated array of partners, we are focused on driving development of the RISC-V ecosystem through our DeepComputing laptops, pads, workstations, AI speakers and routers, as well as our BravoMonster autonomous remote-control toys and real-world vehicles.

Continue ReadingDeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop
Read more about the article Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension

Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension

Hsinchu, Taiwan – Oct 21, 2024 – Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announces the AndesCore™ 46-series processor family with 4 members. The first member, AX46MPV, a new 64-bit multicore superscalar vector processor IP, is the third generation of the award-winning Andes Vector core. While it maintains the same 8-stage dual-issue pipeline as its predecessor AX45MPV, it incorporates numerous new features such as dual load/store units, private L2 cache, an extended VLEN, Andes Matrix Multiply Extension, and RVA22 profile support. Except vector and matrix support, the second member, AX46MP, has the exact same features as the AX46MPV while the third member, A46MP, and fourth member, A46MPV, are the 32-bit versions of AX46MP and AX46MPV. This makes the 46-series ideal for network processors running Linux, high-performance embedded controllers requiring high memory throughput, and large-scale AI/ML applications.

The AX46MPV enhances SpecInt2006 performance by over 15% compared to the previous generation AX45MPV, thanks to its newly designed memory subsystem. The private L2 cache significantly reduces memory latency while the dual load/store engine eliminates memory bottlenecks in memory-bound computation kernels. It supports up to 16 cores in the same cluster, featuring cache coherence and a shared L3 cache with doubled capacity of the AX45MPV. Additionally, the AX46MPV provides TrustZone-level security with ePMP and IOPMP, accompanied by a pre-integrated software solution.

The AX46MPV introduces several enhancements for AI/ML, including longer 2048-bit vectors, new Andes Matrix Extensions to efficiently speed up GEMM performance, and greatly improved High-Bandwidth Vector Memory (HVM) interface supporting outstanding requests and out-of-order responses. A high-performance HVM controller serving up to 16 cores and DMA accesses with 64 memory banks is optional for licensing. The AX46MPV now also includes BF16 full arithmetic mode as a standard feature. Additionally, the award-winning Andes Automated Custom Extension™ (ACE) is available in the 46-series, featuring customized vector instructions (ACE_RVV) with enhanced pipeline and Streaming Port (ASP).  

“We are thrilled to introduce the 3rd generation of the Andes Vector series, further strengthening our leadership in the AI SoC market,” said Dr. Charlie Su, President and CTO of Andes Technology. “Our NX27V and AX45MPV have been highly successful in high-performance AI SoC applications. The AX46MPV, boosted with both compute performance and memory bandwidth, is intended to bring the new-generation AI SoCs to the next level of compute density. Additionally, with enhanced capabilities in Linux, security, and AIoT, the highly configurable 46-series is a well-rounded solution with balanced performance, power, and area”

The AndesCore™ 46-series processor IP’s, 64-bit AX46MP(V) and 32-bit A46MP(V), can be configured from one core up to 16 cores. It is to be available for lead customers in Q1 2025 through the early access program and for general customers in Q2 2025. For further information about the Andes 46 series and Vector processors, please contact Andes Technology.

About Andes Technology

Nineteen years in business and a founding premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

Continue ReadingAndes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension
Read more about the article Andes Announces the AndesCore™ AX66 supporting RVA23, Multi-cluster, Hypervisor and Android

Andes Announces the AndesCore™ AX66 supporting RVA23, Multi-cluster, Hypervisor and Android

Hsinchu, Taiwan — Oct 18, 2024 — Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announces the AndesCore™ AX66 out-of-order superscalar multicore processor IP supporting the RVA23 profile. The AX66 is the 2nd member of the high-performance out-of-order AX60 series. Built on the success of the AX65 with the same 13-stage pipeline, 4-wide decode, and 8-wide out-of-order execution, the AX66 introduces many new features, including Vector and Vector Crypto support, Hypervisor and AIA, Multi-Cluster support with CHI, and RVA23 profile support. AX66’s versatile capabilities on performance scalability, multimedia, security, and virtualization makes it an ideal main processor in high-performance Linux and Android applications such as edge/data center AI, infotainment, networking, and vision/camera applications.

The AX66 boosts the SpecInt2006 performance over the 1st generation AX65 by more than 15%. Each core has 64KB private L1 instruction and data caches and up to 1MB private L2 cache, and each cluster contains up to 8 cores and a shared L3 cache up to 32MB. Besides the IO coherence interface already in the AX65, the AX66 adds a Coherence Hub Interface (CHI) for multi-cluster coherence. With the CHI interface support, we can use much more AX66 CPUs to work together in the same cache-coherent domain.  Together with the Hypervisor, AIA and optional IOMMU technologies, the AX66 can fully virtualize the entire multi-cluster CPU subsystem for resource sharing and security. Moreover, the AX66 supports the RISC-V standard external debug and instruction trace interfaces to facilitate fast system development, analysis and debugging.

“We are excited to announce our 2nd member of the top-of-the-line AX60 series, to further expand our portfolio,” said Dr. Charlie Su, President and CTO of Andes Technology. “We have added numerous features to the AX66, enabling its usage across a wide range of applications. With the RVV support, the AX66 can now handle more advanced AI/ML and multimedia applications. The inclusion of the Vector Crypto extension and the optional IOMMU provides the security capability for a modern day platform system. Additionally, the Hypervisor, AIA, CHI interface support make the AX66 suitable for the data center network applications such as Smart NIC or Data Processing Unit(DPU), and edge servers or devices running containerized applications. The inclusion of the RVA23 profile allows the AX66 to run Android OS on wearables, POS terminals, digital signage, and TV set-top boxes. We anticipate the AX66 to further penetrate high-end mainstream markets.”

The AndesCore™ AX66 is to be available for lead customers in Q4 2024 through the early access program and for general customers in 2025. For further information about the AX66 and the AX60 series processors, please contact Andes Technology.

 

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, automotive and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com . Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

Continue ReadingAndes Announces the AndesCore™ AX66 supporting RVA23, Multi-cluster, Hypervisor and Android
Read more about the article Resiltech與晶心科技宣佈合作 為晶心車規級RISC-V處理器IP提供先進的STL解決方案

Resiltech與晶心科技宣佈合作 為晶心車規級RISC-V處理器IP提供先進的STL解決方案

【義大利蓬泰代拉及台灣新竹】— 2024年10月17日 — 知名的全方位安全解決方案與服務供應商Resiltech與高效能、低功耗RISC-V處理器核心領導供應商晶心科技欣然宣佈雙方將展開策略性合作，為晶心的車規級RISC-V處理器IP提供先進的軟體測試函式庫（STL）解決方案。

這項合作結合了晶心科技先進RISC-V處理器IP的專業技術與Resiltech開發強大STL解決方案的豐富經驗，雙方共同致力於提升汽車電子系統的安全性和可靠性。

不僅如此，此次合作重點在於協助Resiltech開發針對晶心科技的車規級處理器IP進行安全診斷分析的先進STL。雙方攜手推出的產品確保了嚴謹的故障檢測與緩解，並為汽車原廠設備製造商（OEM）和一級供應商（Tier-1）提供可靠且安全的處理器解決方案。

Resiltech STL的設計目的是簡化目標系統的安全認證流程，無需額外操作即能提供專為目標晶片量身定做的預認證產品，並配合簡單快速的軟體整合策略，提供即時支援，協助系統安全整合。

晶心科技致力於提供符合汽車功能安全標準的RISC-V IP，並於2020年通過了ISO-26262 ASIL-D的系統開發流程認證。自那時起，晶心推出了25-SE系列處理器，包括N25F-SE及D25F-SE，這些產品已經完全符合ASIL-B標準，並贏得了十多個客戶合作項目。其中有些客戶已經進入量產階段，並藉助晶心的產品實現了SoC層級的ISO-26262認證。此外，晶心計劃在未來幾個月內發布完全符合ISO-26262 ASIL-D標準認證的處理器，包含D45-SE和D23-SE。

「我們很高興與Resiltech合作，為我們的車規級RISC-V IP帶來增強的安全功能。」晶心科技市場處副處長姜新雨說道。「這次合作彰顯了我們為客戶提供最先進且可靠的汽車應用解決方案的堅定承諾。」

Resiltech的安全解決方案總監Francesco Rossi補充道：「我們在STL開發方面的專業知識與晶心科技創新的處理器IP相得益彰。我們攜手為汽車產業提供了一個全面的解決方案，不僅符合，甚至超越了現代車輛嚴格的安全要求。」

這次合作是提升汽車電子系統安全性的重大里程碑，並為下一代智慧安全車輛開啟了新局面。

關於晶心科技（Andes Technology）
晶心科技股份有限公司於2005年成立於新竹科學園區，2017年於臺灣證交所上市（TWSE: 6533 SIN: US03420C2089; ISIN: US03420C1099）。晶心是RISC-V國際協會的創始首席會員，也是第一家推出商用RISC-V向量處理器的主流CPU供應商。為滿足當今電子設備的嚴格要求，晶心提供可配置性高的32/64位元高效能CPU核心，包含DSP、FPU、Vector、超純量（Superscalar）、亂序執行（Out-of-Order）、多核心及車用系列，可應用於各式SoC與應用場景。晶心並提供功能齊全的整合開發環境和全面的軟/硬體解決方案，可説明客戶在短時間內創新其SoC設計。截至2023年底，嵌入AndesCore™的SoC累積總出貨量已達140億顆。更多關於晶心的資訊，請參閱晶心官網https://www.andestech.com。追蹤晶心最新消息：LinkedIn、Facebook、X、Bilibili以及YouTube。

關於 Resiltech
ResilTech擁有超過15年的經驗，致力為關鍵系統領域的客戶提供最先進的安全與防護解決方案及服務。此外，ResilTech將自身領域專業知識與研發能力相互結合，自創立以來持續積極參與國內外的研發項目。該公司是全球領先的軟體測試函式庫（STL）供應商，針對多種處理節點提供解決方案，並正致力於成為RISC-V生態系統中的STL主要供應商。如需了解更多資訊，請訪問 http://www.resiltech.com。

Continue ReadingResiltech與晶心科技宣佈合作 為晶心車規級RISC-V處理器IP提供先進的STL解決方案
Read more about the article TASKING宣布為晶心科技提供符合ASIL功能安全（FuSa）標準的汽車 RISC-V IP的編譯器支援

TASKING宣布為晶心科技提供符合ASIL功能安全（FuSa）標準的汽車 RISC-V IP的編譯器支援

使SoC設計團隊和汽車軟體開發人員能夠建立最佳化且可認證的軟體解決方案。

德國慕尼黑 – 2024年 8月19日 – TASKING 很榮幸地宣布其符合ISO 26262（功能安全）和ISO/SAE 21434（網絡安全）標準的編譯器現已完全支援晶心經過功能安全（FuSa）認證的RISC-V IP。這一進展擴展了TASKING涵蓋編譯、除錯、效能調校、時序與覆蓋分析工具的RISC-V工具套件，為汽車系統開發提供了全面的解決方案。

這一里程碑在幫助SoC設計團隊和汽車軟體開發人員打造高度優化且基於可認證的RISC-V解決方案方面取得了重大進展。新推出的RISC-V編譯器符合ASIL-D標準，無縫支持已通過和即將通過功能安全（FuSa）認證的晶心RISC-V核心。值得注意的是，該編譯器能夠適應RISC-V ISA及其擴展，包括晶心特定的擴展（Andes-specific extensions），確保針對目標設備進行動態優化，從而提升效率和性能。

晶心科技於2022年推出了全球首款完全符合ISO-26262標準的RISC-V核心N25F-SE，在汽車市場上取得了非凡的里程碑。接著，晶心推出經ASIL-B認證的D25F-SE，配備RISC-V SIMD/DSP P-extension (draft)支援，可在單指令中高效處理多個資料。展望未來，晶心科技將推出符合ASIL-D標準的處理器，包括精簡且安全的D23-SE、高性能的D45-SE以及適用於ADAS應用的AX60系列核心。這些進展彰顯了晶心為多樣化的汽車應用提供客制化解決方案的能力，凸顯了其在汽車RISC-V IP市場的領先專業知識。

「AndesCore™ RISC-V IP已通過ISO 26262認證，提供了可靠的汽車處理器解決方案組合，為晶片開發提供無與倫比的靈活性和效率優勢。」晶心科技市場處副處長姜新雨表示。「我們與TASKING的合作使汽車行業的客戶能夠加快開發流程，增強RISC-V安全關鍵應用的效能和穩健性。」

談到這次合作，TASKING的RISC-V負責人Gerard Vink熱情的表示：「我們很高興能與晶心科技及其生態系伙伴合作。我們的工具與晶心RISC-V IP從虛擬原型到晶片實現的開發平台上之無縫互通性，突顯了我們為SoC開發團隊提供全面生命週期支援的承諾。利用TASKING先進的功能安全（FuSa）和網路安全流程，我們的用戶可以加快合規工作，加速基於 RISC-V 的汽車軟體解決方案的上市時間。」

關於晶心科技
晶心科技股份有限公司于2005年成立於新竹科學園區，2017年於臺灣證交所上市 (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099)。晶心是RISC-V國際協會的創始首席會員，也是第一家推出商用RISC-V向量處理器的主流CPU供應商。為滿足當今電子設備的嚴格要求，晶心提供可配置性高的32/64位元高效能CPU核心，包含DSP、FPU、Vector、超純量  (Superscalar)、亂序執行  (Out-of-Order)、多核心及車用系列，可應用於各式SoC與應用場景。晶心並提供功能齊全的整合開發環境和全面的軟/硬體解決方案，可幫助客戶在短時間內創新其SoC設計。截至2023年底，Andes-Embedded™ SoC累計出貨量已超過140億顆。 欲瞭解更多資訊，請訪問  https://www.andestech.com。請立即透過LinkedIn、X、 Bilibili以及YouTube追蹤晶心最新消息。

關於 TASKING
TASKING是一家總部位於德國慕尼黑的領先開發工具供應商，為多核心架構提供高效能、高品質、以安全和保障為導向的嵌入式軟體開發工具。
汽車製造商和供應商以及世界各地的鄰近市場都使用TASKING的開發工具來實現安全關鍵領域的高性能應用。
TASKING的嵌入式軟體開發解決方案為您的整個軟體開發過程提供業界領先的生態系統。每款TASKING編譯器都針對特定架構設計並滿足您所在行業，包括汽車、工業、電信和資料通訊的特定要求。
作為高品質、功能和安全相容的嵌入式軟體開發工具領域公認的領導者，TASKING 使您能夠透過針對業界領先的微處理器和微控制器的編譯器、偵錯工具和RTOS支援來建立具有一流大小和性能的程式碼。
自2021年2月以來，TASKING的大部分股份由金融投資者FSN Capital擁有，該投資者在成功進行業務分拆後將集團置於長期增長軌道上。欲了解更多資訊，請訪問 www.tasking.com 或在 LinkedIn 上追蹤我們：https://www.linkedin.com/company/tasking-inc。

Continue ReadingTASKING宣布為晶心科技提供符合ASIL功能安全（FuSa）標準的汽車 RISC-V IP的編譯器支援
Read more about the article 晶心科技與Arteris合作加速RISC-V SoC的採用

晶心科技與Arteris合作加速RISC-V SoC的採用

重點：
– 晶心科技與 Arteris 的合作旨在支持共同客戶更多地採用 RISC-V SoC。
– 重點關注: 消費性電子、通訊、工業應用和人工智慧等廣泛市場的高性能/低功耗RISC-V設計。
– 此次合作展示了晶心領先的RISC-V處理器IP和Arteris互連IP於晶片中整合優化的解決方案。

加利福尼亞州坎貝爾 – 2024 年 8 月 15 日 – 專注於加速系統單晶片（SoC）創建的領先系統IP提供商Arteris (Nasdaq: AIP)，與高效率、低功耗、32/64 位元 RISC-V 處理器核心的領先供應商和 RISC-V 國際協會創始首席成員晶心科技（TWSE: 6533），今天宣布雙方建立合作夥伴關係，共同推動在人工智慧、5G、網絡、電信、儲存、AIoT和太空應用領域中基於 RISC-V 的 SoC設計創新。

晶心QiLai RISC-V平台是配備QiLai SoC的開發板，採用晶心RISC-V處理器IP以及用於晶片上網路連接的Arteris FlexNoC互連IP。QiLai SoC整合了2.2 GHz的64位晶心AX45MP多核處理器（四核於單一叢集）和1.5 GHz的NX27V向量處理器，使用Arteris的晶片上網路（NoC）互連IP，並包含PCIe、DDR、SRAM和通用I/O的子系統，這些子系統使用AMBA AXI協議。支援軟體包括OpenSUSE Linux發行版、AndeSight™工具鏈、AndeSoft™軟體堆疊（software stacks）和用於將AI/ML模型轉換為可執行文件的AndesAIRE™ NN SDK。

「儘管AndesCore™ AX45MP和NX27V處理器已被廣泛使用，我們仍然很高興看到QiLai SoC在新專案上能成功。」晶心科技總經理暨技術長蘇泓萌博士表示。「Arteris NoC IP是QiLai SoC中實現靈活、高性能、高階層連接（top-level connectivity）的最佳選擇。QiLai平台增強了RISC-V軟體的快速開發和評估，加速了RISC-V生態系統的擴展。」

「我們很高興能與晶心科技合作，支持QiLai平台的互通性，進一步加速RISC-V技術被主流應用採用。」Arteris首席行銷長Michal Siwinski表示。「我們的合作支持我們成為SoC的創新推動力，使我們的共同客戶能夠高效地專注於實現未來的創新突破。」

Arteris的非快取一致性FlexNoC NoC IP和快取一致性Ncore NoC IP提供可擴展、低延遲和高能效的晶片內通信，從而在複雜的 SoC 設計中實現卓越的性能。這項技術促進了高性能、低功耗CPU IP的整合，增強系統功能和互通性，尤其是在快速增長的RISC-V生態系統中。這種可配置和適應性強的互聯解決方案可與各種組件無縫連接，以降低風險並加速上市時間。透過連接經過充分測試的CPU IP模塊，系統設計師可以利用Arteris的NoC IP來提升下一代SoC的可靠性和品質。

客戶可以透過電子郵件 sales@andestech.com 向晶心科技申請包含Andes QiLai RISC-V平台的開發套件。有關合作夥伴關係和各自產品的更多資訊，請聯繫  info@arteris.com 和info@andestech.com 。

關於Arteris
Arteris是當今電子系統中加速系統單晶片（SoC）開發的領先系統IP供應商。Arteris的片上網路（NoC）互連IP和SoC整合自動化技術可實現更高的產品效能、更低的功耗和更快的上市時間，提供更好的SoC經濟效益，使其客戶可以專注於構思下一步的創新。了解更多資訊，請訪問 arteris.com。

關於晶心科技
晶心科技股份有限公司于2005年成立於新竹科學園區，2017年於臺灣證交所上市 (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099)。晶心是RISC-V國際協會的創始首席會員，也是第一家推出商用RISC-V向量處理器的主流CPU供應商。為滿足當今電子設備的嚴格要求，晶心提供可配置性高的32/64位元高效能CPU核心，包含DSP、FPU、Vector、超純量  (Superscalar)、亂序執行  (Out-of-Order)、多核心及車用系列，可應用於各式SoC與應用場景。晶心並提供功能齊全的整合開發環境和全面的軟/硬體解決方案，可幫助客戶在短時間內創新其SoC設計。截至2023年底，Andes-Embedded™ SoC累計出貨量已超過140億顆。 欲瞭解更多資訊，請訪問  https://www.andestech.com。請立即透過LinkedIn、X、 Bilibili以及YouTube追蹤晶心最新消息。


© 2004-2024 Arteris, Inc. All rights reserved worldwide. Arteris, Arteris IP, the Arteris IP logo, and the other Arteris marks found at https://www.arteris.com/trademarks are trademarks or registered trademarks of Arteris, Inc. or its subsidiaries. All other trademarks are the property of their respective owners.

Continue Reading晶心科技與Arteris合作加速RISC-V SoC的採用