AndeStar™ Architecture

AndeStar™ V5 Families

Andes is a Founding and Premier member of the RISC-V International Association (RVIA). We joined the RISC-V Foundation, the predecessor or RVIA, in 2016. In 2017, Andes released the AndeStar™ V5 architecture, which is fully compatible with the RISC-V instruction set and supports 32-bit and 64-bit processor operations, and started to offer to the market RISC-V processors based on the open, streamlined, modular and scalable RISC-V architecture. The V5 architecture supplements the RISC-V official ISA and functions based on Andes earlier V3 architecture, In addition, Andes is also very active in the RISC-V community and continues to innovate new technologies, such as RVP, RVV, IME, fast interrupt, etc. The 64-bit architecture of V5 enables the development of 64-bit software in the same convenient environment as V3, meeting the needs of new generation SoC designs for memory address capabilities greater than 4GB, such as large-capacity storage devices, large-scale network systems, deep learning and Artificial intelligence applications. SoCs designed using AndeStar™ V5 architecture processors will be able to take full advantages of Andes Technology’s industry-leading high-performance and low-power features, making customer applications more performant when operating at high frequencies.

The Key Features of V5 Architecture

RISC-V Compliance such as:

  • RV32/64IMAC[FDPBKZc] ([]: depends on CPU cores and configurable options)
  • Vector Extension (RVV)
  • RVA profile oriented for AP
  • PLIC and CLIC
  • MMU for Linux applications
  • PMP for TEE isolation
  • RISC-V debug/trace standard
  • Others
 

Custom Features (migrated from V3):

  • Instructions to speed up memory accesses
  • Instructions to speed up branches
  • Handy instructions for zero/sign-extension
  • CoDense™ instructions for code size compaction
  • Automated custom extensions for DSA (Domain-Specific Architecture)
  • SIMD/DSP extension (Andes donated it as the draft for RISC-V P extension)
  • Instruction and Data Local Memory (ILM and DLM)
  • Vectored PLIC with priority-based preemption and configurations
  • StackSafe™ protection for stack overflow and underflow
  • PowerBrake for digitally scaling frequency
  • QuickNap™ for support of fast power-down/wake-up caches
  • Cache management in finer granularity
  • Performance counter 

 

AndeStar™ V3 Families

In 2012, Andes Technology introduced the 16/32-bit hybrid instruction set architecture AndeStar™ V3. For benchmarks commonly used in MCUs, the V3’s execution code is on average 20% smaller than the previous generation V2. The introduction of a comprehensive All-C embedded programming design environment has improved interrupt handling mechanisms and enhanced debugging features, significantly reducing the time required for customers to develop and market their products. The V3 also features the unique Andes Custom Extension™ (ACE) framework, allowing customers to easily define their own instructions and create more differentiation. For CoDense™ instructions, further compress the already very small code size, and the V3m/V3m+ is a subset of the V3, enabling even smaller and lower power consumption AndesCore™. The V3 architecture includes an optional Memory Protection Unit (MPU) for running secure RTOS, and an optional Memory Management Unit (MMU) making the V3 series configurable to support a wide range of applications from microcontrollers to Linux-based embedded systems. 

The Key Features of V3 Architecture

Compared with ARM, MIPS, ARC, Power PC and other architectures, RISC-V is more similar to V3 (except R0 is 0), making it easier to upgrade V3 to RISC-V V5:

  • RISC-style register-based instruction set
  • Mixed 16-bit/32-bit instruction width
  • 16-bit instructions as a frequently used subset of 32-bit instructions
  • 32 or 16 integer General Purpose Registers (GPR)
  • Program counter isn’t a GPR
  • No delayed branch
  • No predicated execution
  • No condition code