AndesCore™ N225

Compact and Performance Efficiency 32-bit RISC-V Core

AndesCore™ N225 Overview

  • AndeStar™ V5 Instruction Set Architecture (ISA)
  • Compliant with RISC-V I, M, A, C, B and Zce extensions
  • Andes extensions for performance and code size enhancements
  • 3-stage pipeline optimized for gate count and efficiency
  • 16/32-bit mixable instructions for code density
  • Instruction and read-only caches supported with an external flash controller
  • Branch prediction to speed up control code
  • Enhanced Physical Memory Protection (ePMP) to enhance core security
  • Core-Local Interrupt Controller (CLIC) for fast response, interrupt prioritization and pre-emption and Platform-Level Interrupt Controller (PLIC) for a wide range of cores and system event scenarios
  • Patented CoDense™ technology to compress program code on top of the 16-bit extension
  • Instruction Trace Interface supports RISC-V Processor Trace v2.0
  • StakeSafe™ hardware to measure stack size, and detect runtime overflow/underflow
  • PowerBrake, WFI/WFE (Wait For Interrupt/Event) for power management on different occasions

The AndesCore™ N225 is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications with small gate count, and some dual-issue ability. In addition to commonly used RISC-V IMAC it supports the recently ratified ISA extensions such as B (bit manipulation) and Zce (code size reduction). The N225 implements ePMP to improve core security; and Andes V5 extensions that includes StackSafe™ (for hardware stack protection), CoDense™, PowerBrake and WFI/WFE. The N225 supports both four-wire and two-wire JTAG debug and instruction trace interface for software development. On the performance front, it deploys several configurable options such as dynamic branch prediction, local memories, multiplier optimized for performance or area. Instruction cache or read-only data access is supported with an external cache controller. Moreover, it comes with rich features to ease SoC integration such as CLIC and PLIC for interrupt handling; an AHB-Lite system bus and an AHB-lite low-latency interface; an APB bus for CPU local peripherals, and an AHB-Lite local memory access port for external bus masters.


  • Embedded controller
  • Sensor fusion
  • Small IoT devices
  • Wearable devices
  • Smart home

Block Diagram

Development Tools

  • AndeSight™ Integrated Development Environment (Eclipse-based)
  • AndeShape™ FPGA Development Boards
  • Debugging Hardware

Key Features and Performance

AndeStar™ V5 (RV32I) 32-bit Architecture

Key FeaturesBenefits
RISC-V RV32 I, M, A, C, B, P, and Zce extensions
  • State-of-the art ISA from latest developments in computer architecture
  • Industry standard and open architecture
Andes Extended InstructionsAndes exclusive performance and functionality enhancements
16/32-bit mixable instruction formatFor compact code density
32 general-purpose registersFor performance
Machine (M) and optional User (U) Privilege levelsEmbedded systems with privilege protections

CPU Core

Key FeaturesBenefits
>1.9 DMIPS/MHz, >4.0 CoreMark/MHzSuperior performance-per-MHz
3-stage pipelineOptimized for gate count and efficiency
Static or dynamic branch predicationSpeed up branch control codes
Enhanced Physical Memory Protection (ePMP) up to 32 entriesEnhance core security
Performance monitorsProgram code performance tuning
StackSafe™ hardware stack protection, planned in revision update
  • Easy identification of stack size threshold during development
  • Hardware error detection of stack overflow and underflow at runtime

Multiplier options:

  • Pipelined with 2-cycle latency, or
  • Sequential with 2-bit results per cycle
Option to choose between speed and area according to application's requirements

Power Management

  • PowerBrake technology, planned in revision update
  • WFI(Wait for Interrupt) and WFE(Wait for Event)
Performance throttling to digitally reduce power consumption WFI instruction and WFE CSR for software power control

Memory Subsystems

Key FeaturesBenefits
Unified read-only instruction cache supported with an external AHB cache controllerAccelerating accesses to slow memories

I/D Local Memory

  • Size: Individually configurable from 1KB up to 512MB with ECC protection
  • SRAM or AHB-Lite interface support
  • For deterministic and efficient program execution
  • Flexible size selection to fit diversified needs

Bus interfaces

Key FeaturesBenefits
  • 32-bit AHB-L System Port - synchronous N:1 core-to-bus clock ratio
  • 32-bit AHB-L Low Latency Port
  • 32-bit APB Peripheral Port
  • 32-bit AHB-L Local Memory Access Port
  • System Port with synchronous N:1 core-to-bus clock ratio to provide user-selectable bus interface for optimal efficiency and ease SoC integration
  • Low Latency Port for latency-sensitive peripherals
  • APB interface for private peripherals
  • Local Memory Access Port allows external bus master to access local memory

Core-Local Interrupt Controller (CLIC)

Key FeaturesBenefits
Up to 1002 interrupt sources, and up to 255 interrupt priority levelsAllow core local interrupts to be serviced and prioritized without sharing

Enhanced interrupt features

  • Selective vectoring with priority preemption

  • Support for software-based tail chaining

  • Faster interrupt handling for real-time applications
  • Complete hardware preemption support for faster response
  • Flexible interrupt source interface for simpler SoC design

Platform-Level Interrupt Controller (PLIC)

Key FeaturesBenefits

Implements RISC-V PLIC specification

  • Up to 1023 interrupt sources
  • Up to 255 interrupt priority levels
Interrupt handling for SoC with multiple processors

Enhanced interrupt features

  • Priority-based preemption
  • Selectable edge trigger or level trigger
Complete hardware preemption support

Debug Support

Key FeaturesBenefits
Implements RISC-V debug specificationsSupported by industry debug tool suppliers
2-wire serial or 4-wire JTAGIndustry-standard support
Embedded Debug Module with 2/4/8 triggersFlexible configurations to tradeoff between gate count and debugging capabilities
Optional password-based secure debugEnhanced secure debugging

Trace Support

Key FeaturesBenefits
RISC-V Processor Trace v2.0 supportSupport instruction trace according to RISC-V standard


Frequency (MHz)To be updated
To be updatedTo be updated
Area (mm2)To be updated

* Base configuration, SVT 9-track library, SS corner, 0.81V, -40°C, and with I/O constraint. Power consumption at TT corner, 0.9V, 25°C

Standard Product Package

  • AndesCore™ N225 with AE350 Platform CPU Subsystem
  • Pre-integrated N225, PLIC, shared debug system, and AHB AE350 Platform