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AndesCore™ A46MP(V)
32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
AndesCore™ A46MP(V) Overview (Preliminary)
- 2 different packages with or without vector: A46MPV, A46MP
- in-order dual-issue 8-stage CPU core with up to 256-bit VLEN
- Symmetric multiprocessing up to 16 cores
- Private Level-2 cache
- Shared L3 cache and coherence support
- Dual scalar and vector load/store unit
- Enhanced sharable High bandwidth vector local memory (HVM)
- AndeStar™ V5 Instruction Set Architecture (ISA)
- Compliant to RISC-V RV32 GCBPV + CMO extensions
- Andes performance extension
- Andes CoDense™ extension for further compaction of code size
- support RVA22 mandatory features relevant for RV32 processors
- Separately licensable Andes Custom Extension™ (ACE) for customized scalar and vector instruction
- Branch predication to speed up control code
- Linux-capable Memory Management Unit (MMU)
- Physical Memory Protection (PMP) and programmable Physical Memory Attribute (PPMA)
- Andes-enhanced Platform-Level Interrupt Controller (PLIC) for a wide range of system events and real-time performance
- Multiprocessing up to 16 cores with hardware managed data coherence
- Configurable VPU vector length (VLEN) and datapath length (DLEN)
- BF16 full arithmetic mode for scalar and vector
- Andes Matrix Multiply Extension for fast matrix multiply computation
- Platform-Level Interrupt Controller (PLIC) support with easy arrangement of preemptive interrupts
- ECC or Parity for SRAM error protection
- StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
- Versatile configurations to tradeoff between core size and performance requirements
- PowerBrake and WFI (Wait For Interrupt) for different power saving occasions
AndesCore™ A46MP(V) 32-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture and Andes Matrix Multiply (AMM) extension. It supports RISC-V standard “G (IMA-FD)”, “ZC” compression, “B” bit manipulation, DSP/SIMD ‘P’ (draft), “V” (vector), CMO (cache management) extensions, Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions. It supports all RVA22 profile mandatory ISAs relevant for RV32. It features MMU for Linux based applications, dynamic branch prediction for efficient branch execution, dual-issue of common instruction pairs, level-1 private instruction/data caches, private level-2 cache and local memories for low-latency accesses. The A46MP(V) symmetric multiprocessor supports up to 16 cores and a shared level-3 cache controller. Coherence Manger ensures data coherence among CPU accesses and IO transactions from external bus managers. All caches are non-blocking with prefetch support. The A46MPV have a powerful VPU with up to 256b VLEN and Matrix unit, is excellent for computations involving large arrays of data.
Development Tools
- AndeSight™ Integrated Development Environment (Eclipse-based)
- AndeShape™ FPGA Development Boards
- COPILOT: Automation tool for Andes Custom Extension™
- AndesClarity™: Processor Pipeline Analyzer and Visualizer
- AndeSoft™ NN Library: Optimized for RISC-V DSP/SIMD and Vector extension
Key Features and Performance
AndeStar™ V5 Architecture
Key Features | Benefits |
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RISC-V RV32 GCBPV+CMO Support all RVA22 mandatory features relevant for RV32 |
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Andes Extended Instructions | Andes exclusive performance and functionality enhancements |
MMU and Sv32 virtual memory translation | For Linux and advanced operating systems with protection between kernel and user program |
32-Bit CPU architecture | High performance vector core with small code size and gate count |
Machine (M), User (U) and Supervisor (S) Privilege levels | Full privilege protections |
CPU Core
Key Features | Benefits |
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>6.3 CoreMark/MHz, >3.9 DMIPS/MHz, >4.3 SpecInt2006/Ghz | Superior performance-per-MHz |
8-stage in-order superscalar pipeline | Superior performance-efficiency, while allowing for high speeds |
Extensive branch predication features
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MMU (Memory Management Unit)
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Physical Memory Protection (PMP), configurable up to 32 regions | Basic read/write/execute memory protection with minimum cost |
Programmable Physical Memory Attribute (PMA), configurable up to 16 regions | Configurable memory attributes:
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Performance monitors | Program code performance tuning |
StackSafe™ hardware stack protection |
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PowerBrake technology | Performance throttling to digitally reduce power consumption |
* DMIPS/MHZ follow Dhrystone’s no-inline ground rules, best performances
Memory Subsystems
Key Features | Benefits |
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Level-1 I-Cache & D-Cache
Level-2 Private Unified Cache
Level-3 Shared Cache
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ILM & DLM
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HVM
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Optional ECC error protection with SRAM interface | Code and data integrity protection |
Bus Manager port: AXI with 128/256-bit data, I/D joint or separate bus | High throughput with wide data path |
BUS Subordinate Port: AXI with 128/256-bit data, for ILM/DLM accesses | Efficient data transfer between CPU and SoC masters |
Core/bus clock ratio of N:1 | Simplified SoC integration |
Multicore Cache Coherence
Key Features | Benefits |
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Vector Processing Unit (VPU)
Key Features | Benefits |
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| Standard and Custom RISC-V vector support |
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Andes Matrix Multiply Extension (AMM)
Key Features | Benefits |
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| Accelerate AI computation |
Platform-Level Interrupt Controller (PLIC)
Key Features | Benefits |
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Implements RISC-V PLIC specification
| Interrupt handling for SoC with multiple processors |
Enhanced interrupt features
| Complete hardware preemption support |
Debug Support
Key Features | Benefits |
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Implements RISC-V debug specifications ver 1.0 | Supported by industry debug tool suppliers |
JTAG Debug Port | Industry-standard support |
Embedded Debug Module with up to 8 triggers | Flexible configurations to tradeoff between gate count and debugging capabilities |
Exception redirection support | Entering debugger upon selected exceptions without using breakpoints |
RISC-V Trace 1.0 Instruction Trace interface | Supported by Andes tools |