AndesCore™ D45 Overview
- 32-bit in-order dual-issue 8-stage pipeline CPU architecture
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- DSP/SIMD extensions
- Floating point extensions
- Andes extensions, architected for performance and functionality enhancements
- 16/32-bit mixable instruction format for compacting code density
- Advanced low power branch predication to speed up control code
- Return Address Stack (RAS) to accelerate procedure returns
- Physical Memory Protection(PMP), and programmable Physical Memory Attribute (PMA)
- MemBoost for heavy memory transactions
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Enhancement of vectored interrupt handling for real-time performance
- Advanced CoDense™ technology to reduce program code size
The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructions, and “N” for user-level interrupts. It is capable of delivering high performance and operating at high frequency and high performance. D45 is also equipped with comprehensive SIMD/DSP instructions that can boost the performance of voice, audio, image and signal processing. Its “FD” extensions support IEEE754-compliance single and double precision floating point instructions as well. It incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. In addition, D45 features advanced low power branch prediction mechanism for efficient branch execution, instruction and data caches, local memories, and ECC error protection. It also includes vectored and preemptive interrupt controller to serve diversified system events, AXI 64-bit bus, rich power management, and JTAG debug and trace interface for software development support.
Applications
- Networking and Communications
- ADAS
- Video and Image Processing
- Advanced Industry Controller
- Smart wireless switch/router
Block Diagram
Development Tools
- AndeSight™ IDE (Eclipse-based)
- Compiler, Debugger, Profiler, Register Bit-field Display/Update, RTOS Awareness, and more
- Tested platforms: Windows and Linux , single- or multi-user installation
- Andes BSP
- Optimized DSP library
- Demo examples and sample projects
- RTOSes
- Open-source: FreeRTOS, Zephyr, RT-Thread
- Commercial: μC/OS-II, ThreadX,
- FPGA Development Boards
- AndeShape™ ADP-XC7 (full-featured)
- Debugging Hardware
- AICE-MICRO and AICE-MINI+
Key Features and Performance
AndeStar™ V5 Architecture
| Key Features | Benefits |
|---|---|
| RISC-V RV32GCPN ISA |
|
| RISC-V P-extension (draft) DSP/SIMD instructions with versatile operations | Boost the performance of voice, audio, image and signal processing |
| RISC-V single and double precision floating point instruction | Accelerate the processing of high precision arithmetic |
| Andes Extended Instructions | Andes exclusive performance and functionality enhancements |
| 16/32-bit mixable instruction format | For compact code density |
| 32 general-purpose registers | For better code size and performance |
| Machine (M), User (U) and Supervisor (S) Privilege levels | For Linux and advanced operating systems with protection between kernel and user programs |
CPU Core
| Key Features | Benefits |
|---|---|
| 5.66 Coremark/MHz, 2.96 DMIPS/MHz* | Excellent performance-per-MHz |
| 8-stage dual-issue in-order pipeline | Superior performance-efficiency, while allowing for high speeds |
Extensive branch predication features
|
|
| Physical Memory Protection (PMP), 16 regions | Basic read/write/execute memory protection with minimum cost |
| Programmable Physical Memory Attribute (PMA), 16 regions | Configurable memory attributes:
|
| Performance monitors | Program code performance tuning |
Multiplier options
| Option to choose between speed and area according to application's requirements |
| PowerBrake technology | Performance throttling to digitally reduce power consumption |
| StackSafe™ hardware stack protection |
|
| QuickNap™ technology | Fast power-down/wake-up support for caches |
* BSP v5.1.0, DMIPS/MHZ follow Dhrystone’s no-inline ground rules, best performances
Memory Subsystems
| Key Features | Benefits |
|---|---|
I-Cache & D-Cache
|
|
ILM & DLM
|
|
| MemBoost – Data Cache Write-Around | Smart cache line allocation policy, for better cache utilization and reduce number of memory accesses |
| MemBoost – Instruction and Data Pre-fetch | Conditionally fill instruction and data caches in advance, for minimum memory access latency |
| MemBoost – Multiple Outstanding Mem. Req. | Issue multiple transactions to data memory sub-system for higher bus utilization, also support out-of-order completion |
| MemBoost – Dedicated I & D Bus Interfaces | Separate instruction and data buses, for instruction and data's own memory transactions |
| Soft-error protection: parity for I-Cache, and ECC for D-Cache, ILM and DLM | Code and data integrity protection |
| Bus master port: AXI with 64-bit data, I/D joint or separate bus | User-selectable bus interface for optimal efficiency |
| Bus save port: AXI with 64-bit data, for ILM/DLM accesses | Efficient data transfer between CPU and SoC masters |
| Core/bus clock ratio of N:1 | Simplified SoC integration |
Platform-Level Interrupt Controller (PLIC)
| Key Features | Benefits |
|---|---|
Implements RISC-V PLIC specification
| Allow individual interrupts to be serviced and prioritized without sharing |
Enhanced interrupt features
|
|
Debug Support
| Key Features | Benefits |
|---|---|
| Implements RISC-V debug specifications | Supported by industry debug tool suppliers |
| JTAG Debug Port | Industry-standard support |
| Embedded Debug Module with up to 8 triggers | Flexible configurations to tradeoff between gate count and debugging capabilities |
| Exception redirection support | Entering debugger upon selected exceptions without using breakpoints |
Performance
| Core, Process | D45, 28nm |
|---|---|
| Frequency (MHz) | 1100 |
| Dynamic power (uW/MHz) | 25.2 |
| Area (mm2) | 0.186 |
* Configured with 32KB instruction and data caches, 16-entry PMP and 16-entry PMA, DSP, without FPU. Using SVT 9-track library, SS corner, 0.81V, -40°C, and with I/O constraint. Power consumption at TT corner, 0.9V, 25°C
Product Package
AndesCore™ D45 Single-core Processor with AE350 AXI Platform
- Pre-integrated D45 single-core CPU subsystem, PLIC, Debug Module, and AXI Platform
