Home | Product & Solutions | AndesCore™ Processors | RISC-V: D45

AndesCore™ D45

AndesCore™ D45 Overview

32-bit in-order dual-issue 8-stage pipeline CPU architecture
AndeStar™ V5 Instruction Set Architecture (ISA)
- Compliant to RISC-V RV32 GCBP little endian:
- RV-GC: Integer, single/double precision floating point and 16-bit extensions
- RV-B Bit manipulation extensions
- RV-P (draft) DSP/SIMD extensions
- Andes V5 performance/code size extensions
16/32-bit mixable instruction format for compacting code density
Advanced low power branch predication to speed up control code
Return Address Stack (RAS) to accelerate procedure returns
Physical Memory Protection(PMP), and programmable Physical Memory Attribute (PMA)
MemBoost for heavy memory transactions
Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
Enhancement of vectored interrupt handling for real-time performance
Advanced CoDense™ technology to reduce program code size

The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructions, “B” bit manipulation, and Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions. A45 equipped with comprehensive SIMD/DSP instructions that can boost the performance of voice, audio, image and signal processing. Its ”B” extensions provide some combination of code size reduction, performance improvement, and energy reduction, and “FD” extensions support IEEE754-compliance single and double precision floating point instructions. D45 incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. Other features include ECC for memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™ and StackSafe™ for software quality improvement, PowerBrake and WFI for power management.

Applications

Networking and Communications
ADAS
Video and Image Processing
Advanced Industry Controller
Smart wireless switch/router

Block Diagram

Development Tools

AndeSight™ IDE (Eclipse-based)
- Compiler, Debugger, Profiler, Register Bit-field Display/Update, RTOS Awareness, and more
- Tested platforms: Windows and Linux , single- or multi-user installation
Andes BSP
- Optimized DSP library
- Demo examples and sample projects
AndesClarity™: Processor Pipeline Analyzer and Visualizer
COPILOT: Automation tool for Andes Custom Extension™
RTOSes
- Open-source: FreeRTOS, Zephyr, RT-Thread
- Commercial: μC/OS-II, ThreadX,
FPGA Development Boards
- AndeShape™ ADP-XC7 (full-featured)
- Xilinx VCU118
Debugging Hardware
- AICE-MICRO and AICE-MINI+

Product Brief

AndesCore™ D45 with Platform Product Brief

Key Features and Performance

AndeStar™ V5 Architecture

Key Features	Benefits
RISC-V RV32GCPB ISA	State-of-the art ISA from latest developments in computer architecture Industry standard and open architecture
Andes Custom Extension™ (ACE) option to create custom instructions for software acceleration	Add custom instruction extensions to facilitate Domain-Specific Architecture/Acceleration (DSA) Boost application performance significantly, at the same time maintain the programmability Powerful constructs are available to define high level instruction ACE design is based on Verilog and C languages which are familiar to the designers The COPILOT tool automatically generates the extended CPU and software toolchain Do not require expertise in processor pipeline to design ACE instructions
Andes Extended Instructions	Andes exclusive performance and functionality enhancements
16/32-bit mixable instruction format	For compact code density
32 general-purpose registers	For better code size and performance
Machine (M), User (U) and Supervisor (S) Privilege levels	For Linux and advanced operating systems with protection between kernel and user programs

CPU Core

Key Features	Benefits
5.67 Coremark/MHz, 2.86 DMIPS/MHz*	Excellent performance-per-MHz
8-stage dual-issue in-order pipeline	Superior performance-efficiency, while allowing for high speeds
Extensive branch predication features Branch Target Buffer (BTB) Branch History Table (BHT) Return Address Stack (RAS)	Branch Target Buffer and Branch History Table to speed up control codes Return Address Stack to speeds up procedure returns
Physical Memory Protection (PMP), configurable up to 32 regions	Basic read/write/execute memory protection with minimum cost
Programmable Physical Memory Attribute (PMA), configurable up to 16 regions	Configurable memory attributes: Memory, I/O, None Cacheable/Non-cacheable Write-back/Write-through Read/write/read & write allocate, no allocate Access fault for non-existent regions
Performance monitors	Program code performance tuning
Multiplier options Fast multiplier: pipelined, 2-cycle Small multipliers: producing 1, 2, 4, or 8 bits per cycle	Option to choose between speed and area according to application's requirements
PowerBrake technology	Performance throttling to digitally reduce power consumption
StackSafe™ hardware stack protection	Easy identification of stack size threshold during development Hardware error detection of stack overflow and underflow at runtime
QuickNap™ technology	Fast power-down/wake-up support for caches

* BSP v5.1.0, DMIPS/MHZ follow Dhrystone's no-inline ground rules, best performances

Memory Subsystems

Key Features	Benefits
I-Cache & D-Cache Size: 8KB to 64KB Set associativity: Direct, 2-way or 4-way	Accelerating accesses to slow memories Flexible cache configurations
ILM & DLM Size: 4KB to 16M SRAM or AXI interface support Bus masters accesses by AXI slave port	For deterministic and efficient program execution Flexible size selection to fit diversified needs
MemBoost	Optimize cache reads and writes to achieve higher bandwidth and lower latency
Soft-error protection: parity for I-Cache, and ECC for D-Cache, ILM and DLM	Code and data integrity protection
Bus master port: AXI with 64/128-bit data, I/D joint or separate bus	User-selectable bus interface for optimal efficiency
Bus save port: AXI with 64/128-bit data, for ILM/DLM accesses	Efficient data transfer between CPU and SoC masters
Core/bus clock ratio of N:1	Simplified SoC integration
64-bit AXI Peripheral Port Interface	For latecny-sensitve peripheral

Platform-Level Interrupt Controller (PLIC)

Key Features	Benefits
Implements RISC-V PLIC specification Up to 1023 PLIC interrupt sources Up to 255 PLIC interrupt priority levels Up to 16 PLIC interrupt targets	Allow individual interrupts to be serviced and prioritized without sharing
Enhanced interrupt features Vectored interrupt dispatch Priority-based preemption Selectable edge trigger or level trigger	Faster interrupt handling for real-time applications Complete hardware preemption support for faster response Flexible interrupt source interface for simpler SoC design

Key Features

Benefits

Implements RISC-V PLIC specification

Up to 1023 PLIC interrupt sources
Up to 255 PLIC interrupt priority levels
Up to 16 PLIC interrupt targets

Allow individual interrupts to be serviced and prioritized without sharing

Enhanced interrupt features

Vectored interrupt dispatch
Priority-based preemption
Selectable edge trigger or level trigger

Faster interrupt handling for real-time applications
Complete hardware preemption support for faster response
Flexible interrupt source interface for simpler SoC design

Debug Support

Key Features	Benefits
Implements RISC-V debug specifications ver 0.13	Supported by industry debug tool suppliers
JTAG Debug Port	Industry-standard support
Embedded Debug Module with up to 8 triggers	Flexible configurations to tradeoff between gate count and debugging capabilities
Exception redirection support	Entering debugger upon selected exceptions without using breakpoints

Trace Support

Key Features	Benefits
Implements RISC-V Trace 1.0 Instruction Trace interface	Supported by Andes tools

Performance

Core, Process	D45, 7nm
Frequency (MHz)	1600
Dynamic power (uW/MHz)	12.1
Area (mm2)	0.036

TSMC 7nm FIN FET ULVT/LVT/SVT, cell height 240nm, High Speed L1 Cache Memory Compiler. Frequency condition: worst: : SSGNP/0.675V/-40oc, typical: TT/0.75v/+85oc. Power and area : typical corner. Configurations: 256-entry BTB, PMP&PMA 16-entry, 32KB I/D$ (no Local Memory), MemBoost, no FPU, with I/O constraint; die area and power are core only, 65% utilization

Product Package

AndesCore™ D45 Single-core Processor with AE350 AXI Platform

Pre-integrated D45 single-core CPU subsystem, PLIC, Debug Module, and AXI Platform