AndesCore™ AX65

Superscalar Out-of-Order Execution Multicore Cluster

AndesCore™ AX65 Overview

  • 64-bit out-of-order 4 wide decode 13-stage CPU core with 128 reordering buffers and 8 functional pipelines
  • Symmetric multiprocessing up to 8 cores
  • Level-2 cache and coherence support
  • AndeStar™ V5 Instruction Set Architecture (ISA)
    • Compliant to RISC-V GCB, scalar cryptography and CMO extensions
    • RVA22 profile compliant
  • 64-bit architecture for memory space over 4GB
  • TAGE Branch predication for highly accurate prediction
  • Linux-capable Memory Management Unit (MMU)
  • Physical Memory Protection (PMP) and latest architecture enhancement extension (ePMP) for access permission controls
  • Andes-enhanced Platform-Level Interrupt Controller (PLIC) for a wide range of system events and real-time performance
  • ECC or Parity for SRAM error protection
  • PowerBrake and WFI (Wait for Interrupt) for different power saving occasions

AndesCore™ AX65 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on AndeStar™ V5 architecture. It supports RISC-V standard “G (IMA-FD)”, “C” 16-bit compression, “B” bit manipulation, “K” (scalar crypto), CMO extensions, and Andes performance enhancements. It features MMU for Linux based applications, TAGE branch prediction for accurate branch execution, 4 wide instruction decode, 8 independent functional pipelines (4 integer, 2 fp, 2 load/store), level-1 instruction/data caches for low-latency accesses. The AX65 symmetric multiprocessor supports up to eight cores and a level-2 cache controller with instruction and data prefetch. Coherence Manger ensures data coherence among CPU accesses and IO transactions from cacheless bus masters. Other features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, and PowerBrake and WFI for power management. 


  • High performance computing
  • Networking
  • Data Storage
  • TV or Setop box

Block Diagram

Development Tools

  • AndeSight™ Integrated Development Environment (Eclipse-based)
  • AndeShape™ FPGA Development Boards

Key Features and Performance

AndeStar™ V5 Architecture

Key FeaturesBenefits
RISC-V RV64 GCB + scalar cryptography + CMO
  • State-of-the art ISA from latest developments in computer architecture
  • Industry standard and open architecture
  • RVA22 profile compliant
Andes Extended InstructionsAndes exclusive performance and functionality enhancements
MMU and Sv39/Sv48 virtual memory translationFor Linux and advanced operating systems with protection between kernel and user program
64-bit CPU architectureEnabling software to utilize the memory spaces far beyond the 4G byte limit of 32-bit CPUs
Machine (M), optional User (U) and Supervisor (S) Privilege levelsprivilege protections

CPU Core

Key FeaturesBenefits
9.25 CoreMark/MHz, 4.9 DMIPS/MHz, 8.25 specint2006/GhzSuperior performance
13-stage out-of-order 4 wide superscalar pipelineSuperior performance-efficiency, while allowing for high speeds

Extensive branch predication features

  • TAgged GEometric length (TAGE) algorithm
  • 2 level Branch Target Buffer (BTB)
  • Return Address Stack (RAS)
  • Most accurate branch prediction algorithm
  • Branch Target Buffer to speed up control codes
  • Return Address Stack to speeds up procedure returns
  • MMU (Memory Management Unit)
  • Sv39, Sv48 virtual-memory systems
  • 16/32-entry fully associative level1 ITLB/DTLB
  • Up to 1024 entry 4-way set-associative L2 TLB
  • Hardware page table walker
  • Virtual memory support for full address space and easy code/data sharing
  • Support for full-featured OS such as Linux
  • Protection of supervisor and user privilege
  • Hardware for fast address translation
Physical Memory Protection (PMP), configurable up to 16 regionsBasic read/write/execute memory protection with minimum cost
16 programmable physical memory attributes (PPMA) regions

Configurable memory attributes:

  • Memory, I/O, None
  • Cacheable/Non-cacheable
  • Write-back/Write-through
  • Read/write/read & write allocate, no allocate
  • Access fault for non-existent regions
Performance monitorsProgram code performance tuning
PowerBrake technologyPerformance throttling to digitally reduce power consumption

Memory Subsystems

Key FeaturesBenefits

Level-1 I-Cache & D-Cache

  • Size: 8KB to 64KB
  • Cache line size: 64 bytes
  • Set associativity: 2-way or 4-way
  • Accelerating accesses to slow memories
  • Flexible cache configurations

Level-2 I/D Unified Cache

  • Configurable from 128KB to 8MB
  • 64-byte cache line size
  • 16-way, pseudo random replacement
  • 2 tag banks, 2 data banks with interleaving
  • Accelerate performance with larger 2nd level cache
  • Flexible selections to meet performance and timing requirements
Optional ECC error protection with SRAM interfaceCode and data integrity protection
Bus master port: AXI with 256 bit data, I/D joint or separate busHigh throughput with wide data path
Core/bus clock ratio of N:1Simplified SoC integration

Multicore Cache Coherence

Key FeaturesBenefits
  • Support up to 8 cores
  • MESI cache coherence protocol
  • 256-bit I/O coherence port for cacheless bus masters
  • Symmetric multicore and L2 cache controller with cache coherence between level-1 (L1) caches and I/O coherence for bus masters without caches
  • Convenient and efficient interface for SoCs with rich I/O transactions

Platform-Level Interrupt Controller (PLIC)

Key FeaturesBenefits

Implements RISC-V PLIC specification

  • Up to 1023 interrupt sources
  • Up to 255 interrupt priority levels
Interrupt handling for SoC with multiple processors

Enhanced interrupt features

  • Priority-based preemption
  • Selectable edge trigger or level trigger
Complete hardware preemption support

Debug Support

Key FeaturesBenefits
Implements RISC-V debug specification v1.0Supported by industry debug tool suppliers
JTAG Debug PortIndustry-standard support
Embedded Debug Module with up to 8 triggersFlexible configurations to tradeoff between gate count and debugging capabilities
Exception redirection supportEntering debugger upon selected exceptions without using breakpoints
RISC-V Trace 1.0 Instruction Trace interfaceSupported by Andes tools

Press Release