AndesCore™ AX45MPV

64-bit RISC-V Multicore Processor with 1024-bit Vector Extension

AndesCore™ AX45MPV Overview

  • 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
  • Symmetric multiprocessing up to 8 cores
  • Level-2 cache and coherence support
  • High bandwidth vector local memory (HVM)
  • AndeStar™ V5 Instruction Set Architecture (ISA)
    • Compliant to RISC-V GCBPV extensions
    • Andes performance extension
    • Andes CoDense™ extension for further compaction of code size
  • Full-arithmetic BF16 vector/scalar instructions with mode bit control
  • Separately licensable Andes Custom Extension™ (ACE) for customized scalar and vector instruction
  • 64-bit architecture for memory space over 4GB
  • Branch predication to speed up control code
  • Linux-capable Memory Management Unit (MMU)
  • Physical Memory Protection (PMP) and programmable Physical Memory Attribute (PPMA)
  • Andes-enhanced Platform-Level Interrupt Controller (PLIC) for a wide range of system events and real-time performance
  • Multiprocessing up to 8 cores with hardware managed data coherence
  • Configurable VPU vector length (VLEN) and datapath length (DLEN)
  • Platform-Level Interrupt Controller (PLIC) support with easy arrangement of preemptive interrupts
  • ECC or Parity for SRAM error protection
  • StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
  • Versatile configurations to tradeoff between core size and performance requirements
  • PowerBrake and WFI (Wait For Interrupt) for different power saving occasions

AndesCore™ AX45MPV 64-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture. It supports RISC-V standard “G (IMA-FD)”, “C” 16-bit compression, “B” bit manipulation, DSP/SIMD ‘P’ (draft), “V” (vector) extensions, and Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions. It features MMU for Linux based applications, dynamic branch prediction for efficient branch execution, dual-issue of common instruction pairs, level-1 instruction/data caches and local memories for low-latency accesses. The AX45MPV symmetric multiprocessor supports up to eight cores and a level-2 cache controller with instruction and data prefetch. Coherence Manger ensures data coherence among CPU accesses and IO transactions from cacheless bus masters. The AX45MPV contains a powerful VPU with up to 1024-bit VLEN and DLEN, and is excellent for computations involving large arrays of data such as computer vision, digital signal processing, image processing, machine/deep learning, and scientific computing. Other features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™ and StackSafe™, and PowerBrake and WFI for power management.


  • Computer vision
  • Digital Signal Processing
  • Image Processing
  • Machine/Deep learning acceleration
  • Scientific Computing

Block Diagram

Development Tools

  • AndeSight™ Integrated Development Environment (Eclipse-based)
  • AndeShape™ FPGA Development Boards
  • COPILOT: Automation tool for Andes Custom Extension™
  • AndesClarity™: Processor Pipeline Analyzer and Visualizer
  • AndeSoft™ NN Library: Optimized for RISC-V DSP/SIMD and Vector extension

Key Features and Performance

AndeStar™ V5 Architecture

Key FeaturesBenefits
  • State-of-the art ISA from latest developments in computer architecture
  • Industry standard and open architecture
Andes Extended InstructionsAndes exclusive performance and functionality enhancements
MMU and Sv39/Sv48 virtual memory translationFor Linux and advanced operating systems with protection between kernel and user program
64-bit CPU architectureEnabling software to utilize the memory spaces far beyond the 4G byte limit of 32-bit CPUs
Machine (M), optional User (U) and Supervisor (S) Privilege levelsEmbedded systems with privilege protections

CPU Core

Key FeaturesBenefits
5.86 CoreMark/MHz, 3.39 DMIPS/MHzSuperior performance-per-MHz
8-stage dual issue in-order superscalar pipelineSuperior performance-efficiency, while allowing for high speeds

Extensive branch predication features

  • Branch Target Buffer (BTB)
  • Branch History Table (BHT)
  • Return Address Stack (RAS)
  • Branch Target Buffer and Branch History Table to speed up control codes
  • Return Address Stack to speeds up procedure returns
  • MMU (Memory Management Unit)
  • Sv39, Sv48 virtual-memory systems
  • 4/8-entry fully associative ITLB/DTLB
  • 32-512-entry 4-way set-associative shared TLB
  • Hardware page table walker
  • Virtual memory support for full address space and easy code/data sharing
  • Support for full-featured OS such as Linux
  • Protection of supervisor and user privilege
  • Hardware for fast address translation
Physical Memory Protection (PMP), configurable up to 32 regionsBasic read/write/execute memory protection with minimum cost
Programmable Physical Memory Attribute (PMA), configurable up to 16 regions

Configurable memory attributes:

  • Memory, I/O, None
  • Cacheable/Non-cacheable
  • Write-back/Write-through
  • Read/write/read & write allocate, no allocate
  • Access fault for non-existent regions
Performance monitorsProgram code performance tuning
StackSafe™ hardware stack protection
  • Easy identification of stack size threshold during development
  • Hardware error detection of stack overflow and underflow at runtime
PowerBrake technologyPerformance throttling to digitally reduce power consumption
QuickNap™ technologyFast power-down/wake-up support for cache

Memory Subsystems

Key FeaturesBenefits

Level-1 I-Cache & D-Cache

  • Size: 8KB to 64KB
  • Cache line size: 64 bytes
  • Set associativity: 2-way or 4-way
  • Accelerating accesses to slow memories
  • Flexible cache configurations

Level-2 I/D Unified Cache

  • Configurable from 128KB to 8MB
  • 64-byte cache line size
  • 16-way, pseudo random replacement
  • 2 or 4 banks
  • Accelerate performance with larger 2nd level cache
  • Flexible selections to meet performance and timing requirements


  • Size: 4KB to 16MB
  • Scalar core access only
  • SRAM interface support
  • Bus masters accessed by AXI slave port
  • For deterministic and efficient program execution
  • Flexible size selection to fit diversified needs


  • Size: 32KB to 4GB
  • Accessible by VPU and scalar core, can also be shared by multiple cores
  • Fast vector access with DLEN data width
  • Slave port for external DMA
  • When MMU is presented, HVM is addressed by MMU translated physical memory, therefore it can also work under Linux
  • Local memory for vector data, especially for AI model, can work with external DMA to hide the latency.
  • High speed direct access


  • Data Cache Write-Around
  • Instruction and Data Prefetch
  • Multiple Outstanding Mem. Req
  • Smart cache line allocation policy, for better cache utilization and reduce number of memory accesses
  • Conditionally fill instruction and data caches in advance, for minimum memory access latency
  • Issue multiple transactions to data memory sub-system for higher bus utilization, also support out-of-order completion
Optional ECC error protection with SRAM interfaceCode and data integrity protection
Bus master port: AXI with 128/256/512-bit data, I/D joint or separate busHigh throughput with wide data path
BUS Slave Port: AXI with 128/256/512-bit data, for ILM/DLM accessesEfficient data transfer between CPU and SoC masters
Core/bus clock ratio of N:1Simplified SoC integration

Multicore Cache Coherence

Key FeaturesBenefits
  • Support up to 8 cores
  • MESI cache coherence protocol
  • 128/256/512-bit I/O coherence port for cacheless bus masters 
  • Symmetric multicore and L2 cache controller with cache coherence between level-1 (L1) caches and I/O coherence for bus masters without caches
  • Convenient and efficient interface for SoCs with rich I/O transactions

Vector Processing Unit (VPU)

Key FeaturesBenefits
  • RISC-V V-extension (RVV) 1.0 spec
  • Custom RVV instructions based on ACE-RVV
  • LMUL supporting 1, 2, 4, 8, 1/2, 1/4, 1/8
  • Standard and Custom RISC-V vector support
  • Vector dual issue
  • Available 2nd multiply-add unit
  • Two vector instructions can be issued at same cycle
  • Up to 2 MAC units for maximum performance
  • Configurable VLEN/DLEN from 128 to 1024 bits with 1:1 or 2:1 ratio
  • Multiple independent vector execution units for parallel execution
  • Dual Independent memory access paths with RVV load/store and Andes Streaming Port (ASP) load/store
  • Addressing a wide range of compute requirements with different area/performance trade-off
  • High Speed memory accesses to CoProcessor memory in addition to the standard memory hierarchy with DLEN data width

Platform-Level Interrupt Controller (PLIC)

Key FeaturesBenefits

Implements RISC-V PLIC specification

  • Up to 1023 interrupt sources
  • Up to 255 interrupt priority levels
Interrupt handling for SoC with multiple processors

Enhanced interrupt features

  • Priority-based preemption
  • Selectable edge trigger or level trigger
Complete hardware preemption support

Debug Support

Key FeaturesBenefits
Implements RISC-V debug specification v1.0Supported by industry debug tool suppliers
JTAG Debug PortIndustry-standard support
Embedded Debug Module with up to 8 triggersFlexible configurations to tradeoff between gate count and debugging capabilities
Exception redirection supportEntering debugger upon selected exceptions without using breakpoints
RISC-V Trace 1.0 Instruction Trace interfaceSupported by Andes tools

*MMU and HVM features are available in 2023 Q4

Press Release on AX45MPV

Product Package