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AndesCore™ AX45MP Multicore

64-bit Multiprocessors with Level-2 Cache-Coherence

AndesCore™ AX45MP Overview

64-bit in-order dual-issue 8-stage pipeline CPU architecture
Symmetric multiprocessing up to 4 cores
Level-2 cache and cache coherence support
AndeStar™ V5 Instruction Set Architecture (ISA). Compliant to RISC-V ISA IMACFDN, with Andes performance/functionality extensions
Floating point extension DSP/SIMD ISA
Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
64-bit architecture for memory space over 4GB
16/32-bit mixable instruction format for compacting code density
Branch predication to speed up control code
Return Address Stack (RAS) to speed up procedure returns
Memory Management Unit (MMU), Physical Memory Protection (PMP) and programmable Physical Memory Attribute (PMA)
Level-1 and level-2 cache controllers with 64-byte cache line size
Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
Enhancement of vectored interrupt handling for real-time performance
Advanced CoDense™ technology to reduce program code size

AndesCore™ AX45MP 64-bit multicore CPU IP is an 8-stage superscalar processor based on AndeStar™ V5 architecture. It supports RISC-V standard “G (IMAC-FD)” extensions, “C” 16-bit compression instructions, DSP/SIMD ‘P’ extension (draft), user-level interrupt ‘N’ extension, and Andes performance/ functionality enhancements for faster memory accesses and branch handling, plus Andes Custom Extension™ (ACE) to add user-defined instructions. It features MMU for Linux based applications, branch prediction for efficient branch execution, level-1 instruction/data caches and local memories for low-latency accesses.

The AX45MP symmetric multiprocessor supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. Coherence manger implements MESI protocol to manage level-1 cache coherence, including I/O coherence for cacheless bus masters. Other AX45MP features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™, StackSafe™ for software quality improvement, and QuickNap™, PowerBrake, and WFI for power management.

AndesCore™ AX25MP Multicore

Applications

High performance application processor
Machine/Deep learning acceleration
Video and image processing
Large-scale network controllers
ADAS/V2X/IVI

Block Diagram

Development Tools

AndeSight™ IDE (Eclipse-based)
- Compiler, Debugger, Profiler, Register Bit-field Display/Update, RTOS Awareness, and more
- Tested platforms: Windows and Linux, single- or multi-user installation
Andes BSP
- Optimized DSP library
- Demo examples and sample projects
RTOSes
- Open-source: FreeRTOS, Zephyr, RT-Thread
- Commercial: ThreadX, μC/OS-II
SMP Linux kernel and platform drivers
COPILOT: Custom-OPtimized Instruction deveLOpment Tool for ACE
FPGA Development Boards
- AndeShape™ ADP-XC7K410
- Xilinx VCU118 and AndeShape™ FMC Modules
- AndeShape™ Board Farm
Debugging Hardware
- AICE-MICRO and AICE-MINI+

Product Brief

AndesCore™ AX45MP with Platform Product Brief

Key Features and Performance

AndeStar™ V5 Architecture

Key Features	Benefits
RISC-V RV64IMACFD instructions	State-of-the art ISA from latest developments in computer architecture Industry standard and open architecture
64-bit CPU architecture	Enabling software to utilize the memory spaces far beyond the 4G byte limit of 32-bit CPUs
RISC-V P-extension (draft) DSP/SIMD instructions with versatile operations	Boost the performance of voice, audio, image and signal processing
RISC-V single and double precision floating point instruction	Accelerate the processing of high precision arithmetic
Andes Extended Instructions	Andes exclusive performance and functionality enhancements
Andes Custom Extension™ (ACE) option to create customized instructions for software acceleration	Add customized instruction extensions to facilitate Domain-Specific Architecture/Acceleration (DSA) Boost application performance significantly, at the same time maintain the programmability Powerful constructs are available to define high level instruction ACE design is based on Verilog and C languages which are familiar to the designers The COPILOT tool automatically generates the extended CPU and software toolchain Do not require expertise in processor pipeline to design ACE instructions
16/32-bit mixable instruction format	For compact code density
32 general-purpose registers	For better code size and performance
Machine (M), User (U) and Supervisor (S) Privilege levels	For Linux and advanced operating systems with protection between kernel and user programs

CPU Core

Key Features	Benefits
5.50 Coremark/MHz, 3.14 DMIPS/MHz*	Superior performance-per-MHz
8-stage in-order superscalar pipeline	Superior performance-efficiency, while allowing for high speeds
Extensive branch predication features Branch Target Buffer (BTB) Branch Histroy Table (BHT) Return Address Stack (RAS)	Branch Target Buffer and Branch History Table to speed up control codes Return Address Stack to speeds up procedure returns
MMU (Memory Management Unit) Sv39, Sv48 virtual-memory systems 4/8-entry fully associative ITLB/DTLB 32-512-entry 4-way set-associative shared TLB Hardware page table walker	Virtual memory support for full address space and easy code/data sharing Support for full-featured OS such as Linux Protection of supervisor and user privilege Hardware for fast address translation
Physical Memory Protection (PMP), 16 regions	Basic read/write/execute memory protection with minimum cost
Programmable Physical Memory Attribute (PMA), 16 regions	Configurable memory attributes: Memory, I/O, None Cacheable/Non-cacheable Write-back/Write-through Read/write/read & write allocate, no allocate Access fault for non-existent regions
Performance monitors	Program code performance tuning
StackSafe™ hardware stack protection	Easy identification of stack size threshold during development Hardware error detection of stack overflow and underflow at runtime
Multiplier options Fast multiplier: pipelined, 2-cycle Small multipliers: producing 1, 2, 4, or 8 bits per cycle	Option to choose between speed and area according to application's requirements
PowerBrake technology	Performance throttling to digitally reduce power consumption
QuickNap™ technology	Fast power-down/wake-up support for caches

* BSP v5.1.0, DMIPS/MHZ follow Dhrystone’s no-inline ground rules, best performances

Memory Subsystems

Key Features	Benefits
Level-1 I-Cache & D-Cache Size: 8KB to 64KB Cache line size: 64 bytes Set associativity: 2-way or 4-way	Accelerating accesses to slow memories Flexible cache configurations
Level-2 I/D Unified Cache Configurable from 128KB to 2MB 64-byte cache line size 16-way, pseudo random line replacement 2 tag banks, 2 data banks with interleaving Configurable memory cycles for SRAM timing	Accelerate performance with level-2 memory Flexible selections to meet performance and timing requirements
ILM & DLM Size: 4KB to 16MB SRAM interface support Bus masters accessed by AXI slave port	For deterministic and efficient program execution Flexible size selection to fit diversified needs
MemBoost – Data Cache Write-Around	Smart cache line allocation policy, for better cache utilization and reduce number of memory accesses
MemBoost – Instruction and Data Pre-fetch	Conditionally fill instruction and data caches in advance, for minimum memory access latency
MemBoost – Multiple Outstanding Mem. Req.	Issue multiple transactions to data memory sub-system for higher bus utilization, also support out-of-order completion
Optional ECC error protection with SRAM interface	Code and data integrity protection
Bus master port: AXI with 128-bit data, I/D joint or separate bus	High throughput with wide data path
BUS Slave Port: AXI with 128-bit data, for ILM/DLM accesses	Efficient data transfer between CPU and SoC masters
Core/bus clock ratio of N:1	Simplified SoC integration

Multicore Cache Coherence

Key Features	Benefits
Support up to 4 cores MESI cache coherence protocol Support I/O coherence for cacheless bus masters by 128-bit AXI slave port	Symmetric multicore and L2 cache controller with cache coherence between level-1 (L1) caches and I/O coherence for bus masters without caches High efficient memory transaction for sophisticated Linux SMP

Platform-Level Interrupt Controller (PLIC)

Key Features	Benefits
Implements RISC-V PLIC specification Up to 1023 PLIC interrupt sources Up to 255 PLIC interrupt priority levels Up to 16 PLIC interrupt targets	Allow individual interrupts to be serviced and prioritized without sharing
Enhanced interrupt features Vectored interrupt dispatch Priority-based preemption Selectable edge trigger or level trigger	Faster interrupt handling for real-time applications Complete hardware preemption support for faster response Flexible interrupt source interface for simpler SoC design

Key Features

Benefits

Implements RISC-V PLIC specification

Up to 1023 PLIC interrupt sources
Up to 255 PLIC interrupt priority levels
Up to 16 PLIC interrupt targets

Allow individual interrupts to be serviced and prioritized without sharing

Enhanced interrupt features

Vectored interrupt dispatch
Priority-based preemption
Selectable edge trigger or level trigger

Faster interrupt handling for real-time applications
Complete hardware preemption support for faster response
Flexible interrupt source interface for simpler SoC design

Debug Support

Key Features	Benefits
Implements RISC-V debug specifications	Supported by industry debug tool suppliers
JTAG Debug Port	Industry-standard support
Embedded Debug Module with up to 8 triggers	Flexible configurations to tradeoff between gate count and debugging capabilities
Exception redirection support	Entering debugger upon selected exceptions without using breakpoints

Product Package

AX45MP with 1, 2 or 4 Processor(s) and AE350 Platform

Pre-integrated AX45MP CPU subsystem, PLIC, Debug Module, and AXI PlatformAXI Platform